2  * Copyright (c) 2018-2019 Intel Corporation
4  * SPDX-License-Identifier: Apache-2.0
17  * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18  * each set is further sub-divided into multiple devices, so
93 	((const struct gpio_intel_config *)(_dev)->config)
94 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
140 	struct gpio_intel_data *data = dev->data;  in check_perm()
141 	const struct gpio_intel_config *cfg = dev->config;  in check_perm()
144 	pin_offset = cfg->pin_offset;  in check_perm()
160 	offset = data->pad_base + (raw_pin << 4);  in check_perm()
192 		cfg = dev->config;  in gpio_intel_isr()
193 		data = dev->data;  in gpio_intel_isr()
200 		SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {  in gpio_intel_isr()
201 			cur_mask = int_sts & cb->pin_mask;  in gpio_intel_isr()
204 				__ASSERT(cb->handler, "No callback handler!");  in gpio_intel_isr()
205 				cb->handler(dev, cb, cur_mask);  in gpio_intel_isr()
217 	const struct gpio_intel_config *cfg = dev->config;  in gpio_intel_config()
218 	struct gpio_intel_data *data = dev->data;  in gpio_intel_config()
221 	/* Only support push-pull mode */  in gpio_intel_config()
223 		return -ENOTSUP;  in gpio_intel_config()
226 	pin = k_array_index_sanitize(pin, cfg->num_pins + 1);  in gpio_intel_config()
228 	raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);  in gpio_intel_config()
231 		return -EINVAL;  in gpio_intel_config()
235 	reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in gpio_intel_config()
261 		/* clear TX disable bit */  in gpio_intel_config()
264 		/* set TX disable bit */  in gpio_intel_config()
268 	/* pull-up or pull-down */  in gpio_intel_config()
278 	/* IO Standby state to TX,RX enabled */  in gpio_intel_config()
293 	const struct gpio_intel_config *cfg = dev->config;  in gpio_intel_pin_interrupt_configure()
294 	struct gpio_intel_data *data = dev->data;  in gpio_intel_pin_interrupt_configure()
298 	/* no double-edge triggering according to data sheet */  in gpio_intel_pin_interrupt_configure()
300 		return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
303 	pin = k_array_index_sanitize(pin, cfg->num_pins + 1);  in gpio_intel_pin_interrupt_configure()
305 	raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);  in gpio_intel_pin_interrupt_configure()
308 		return -EINVAL;  in gpio_intel_pin_interrupt_configure()
316 	reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in gpio_intel_pin_interrupt_configure()
338 			return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
349 			return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
360 		/* invert pin for active low triggering */  in gpio_intel_pin_interrupt_configure()
384 	struct gpio_intel_data *data = dev->data;  in gpio_intel_manage_callback()
386 	return gpio_manage_callback(&data->cb, callback, set);  in gpio_intel_manage_callback()
393 	const struct gpio_intel_config *cfg = dev->config;  in port_get_raw()
394 	struct gpio_intel_data *data = dev->data;  in port_get_raw()
405 		pin = find_lsb_set(mask) - 1;  in port_get_raw()
407 		if (pin >= cfg->num_pins) {  in port_get_raw()
413 		raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);  in port_get_raw()
419 		reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in port_get_raw()
433 	const struct gpio_intel_config *cfg = dev->config;  in port_set_raw()
434 	struct gpio_intel_data *data = dev->data;  in port_set_raw()
438 		pin = find_lsb_set(mask) - 1;  in port_set_raw()
440 		if (pin >= cfg->num_pins) {  in port_set_raw()
446 		raw_pin = GPIO_RAW_PIN(pin, cfg->pin_offset);  in port_set_raw()
452 		reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in port_set_raw()
527 	struct gpio_intel_data *data = dev->data;  in gpio_intel_init()
534 	 * into 32-pin blocks so each block has a GPIO driver instance.  in gpio_intel_init()
538 	 * So when mapping the address, the lowest 8-bit needs to be  in gpio_intel_init()
543 	const struct gpio_intel_config *cfg = dev->config;  in gpio_intel_init()
545 	device_map(&data->reg_base,  in gpio_intel_init()
546 		   cfg->reg_base.phys_addr & ~0xFFU,  in gpio_intel_init()
547 		   cfg->reg_base.size,  in gpio_intel_init()
552 	data->pad_base = pad_base(dev);  in gpio_intel_init()