6  * SPDX-License-Identifier: Apache-2.0
37 	if (regs->ACR & FLASH_ACR_DCEN) {  in flush_cache()
38 		regs->ACR &= ~FLASH_ACR_DCEN;  in flush_cache()
40 		 * This bit can be written only when the data cache is disabled  in flush_cache()
42 		regs->ACR |= FLASH_ACR_DCRST;  in flush_cache()
43 		regs->ACR &= ~FLASH_ACR_DCRST;  in flush_cache()
44 		regs->ACR |= FLASH_ACR_DCEN;  in flush_cache()
47 	if (regs->ACR & FLASH_ACR_ICEN) {  in flush_cache()
48 		regs->ACR &= ~FLASH_ACR_ICEN;  in flush_cache()
51 		 * is disabled  in flush_cache()
53 		regs->ACR |= FLASH_ACR_ICRST;  in flush_cache()
54 		regs->ACR &= ~FLASH_ACR_ICRST;  in flush_cache()
55 		regs->ACR |= FLASH_ACR_ICEN;  in flush_cache()
79 	/* if the control register is locked, do not fail silently */  in write_dword()
80 	if (regs->CR & FLASH_CR_LOCK) {  in write_dword()
81 		return -EIO;  in write_dword()
84 	/* Check that no Flash main memory operation is ongoing */  in write_dword()
90 	/* Check if this double word is erased and value isn't 0.  in write_dword()
92 	 * It is allowed to write only zeros over an already written dword  in write_dword()
98 		return -EIO;  in write_dword()
104 	 * "Data cache might be corrupted during Flash memory read-while-write operation"  in write_dword()
106 	if (regs->ACR & FLASH_ACR_DCEN) {  in write_dword()
108 		regs->ACR &= (~FLASH_ACR_DCEN);  in write_dword()
113 	regs->CR |= FLASH_CR_PG;  in write_dword()
116 	tmp = regs->CR;  in write_dword()
122 	/* Wait until the BSY bit is cleared */  in write_dword()
126 	regs->CR &= (~FLASH_CR_PG);  in write_dword()
131 		regs->ACR |= FLASH_ACR_DCRST;  in write_dword()
132 		regs->ACR &= (~FLASH_ACR_DCRST);  in write_dword()
133 		regs->ACR |= FLASH_ACR_DCEN;  in write_dword()
150 	/* Single bank device. Each page is of 2KB size */  in erase_page()
153 	/* L4 series (2K page size) with configurable Dual Bank (default y) */  in erase_page()
154 	/* Dual Bank is only option for 1M devices */  in erase_page()
155 	if ((regs->OPTR & FLASH_OPTR_DUALBANK) ||  in erase_page()
157 		/* Dual Bank configuration (nbr pages = flash size / 2 / 2K) */  in erase_page()
162 		return -ENOTSUP;  in erase_page()
165 	/* L4+ series (4K page size) with configurable Dual Bank (default y)*/  in erase_page()
166 	if (regs->OPTR & FLASH_STM32_DBANK) {  in erase_page()
167 		/* Dual Bank configuration (nbre pags = flash size / 2 / 4K) */  in erase_page()
171 		/* Requires 128 bytes data read. This config is not supported */  in erase_page()
172 		return -ENOTSUP;  in erase_page()
176 	/* if the control register is locked, do not fail silently */  in erase_page()
177 	if (regs->CR & FLASH_CR_LOCK) {  in erase_page()
178 		return -EIO;  in erase_page()
181 	/* Check that no Flash memory operation is ongoing */  in erase_page()
190 	regs->CR |= FLASH_CR_PER;  in erase_page()
192 	regs->CR &= ~FLASH_CR_BKER_Msk;  in erase_page()
195 		regs->CR |= FLASH_CR_BKER;  in erase_page()
197 	regs->CR &= ~FLASH_CR_PNB_Msk;  in erase_page()
198 	regs->CR |= ((page % pages_per_bank) << 3);  in erase_page()
201 	regs->CR |= FLASH_CR_STRT;  in erase_page()
204 	tmp = regs->CR;  in erase_page()
209 	regs->CR &= ~FLASH_CR_PER;  in erase_page()
221 	for (; i <= get_page(offset + len - 1) ; ++i) {  in flash_stm32_block_erase_loop()