Lines Matching +full:8 +full:- +full:bit
5 * SPDX-License-Identifier: Apache-2.0
18 ((flag_u32) >> ROUND_DOWN(LOG2((flag_u32)), 8))
28 #define MCP251XFD_TEF_FIFO_ITEM_SIZE 8
29 #define MCP251XFD_TX_QUEUE_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
32 #define MCP251XFD_RX_FIFO_ITEM_SIZE (4 + 8 + MCP251XFD_PAYLOAD_SIZE)
34 #define MCP251XFD_RX_FIFO_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
82 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
87 #define MCP251XFD_REG_CON_ABAT BIT(27)
98 #define MCP251XFD_REG_CON_TXQEN BIT(20)
99 #define MCP251XFD_REG_CON_STEF BIT(19)
100 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
101 #define MCP251XFD_REG_CON_ESIGM BIT(17)
102 #define MCP251XFD_REG_CON_RTXAT BIT(16)
103 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
104 #define MCP251XFD_REG_CON_BUSY BIT(11)
110 #define MCP251XFD_REG_CON_WAKFIL BIT(8)
111 #define MCP251XFD_REG_CON_PXEDIS BIT(6)
112 #define MCP251XFD_REG_CON_ISOCRCEN BIT(5)
121 #define MCP251XFD_REG_NBTCFG_TSEG2_MASK GENMASK(14, 8)
127 #define MCP251XFD_REG_DBTCFG_TSEG2_MASK GENMASK(11, 8)
131 #define MCP251XFD_REG_TDC_EDGFLTEN BIT(25)
132 #define MCP251XFD_REG_TDC_SID11EN BIT(24)
137 #define MCP251XFD_REG_TDC_TDCO_MASK GENMASK(14, 8)
139 #define MCP251XFD_REG_TDC_TDCO_MIN -64
145 #define MCP251XFD_REG_TSCON_TSRES BIT(18)
146 #define MCP251XFD_REG_TSCON_TSEOF BIT(17)
147 #define MCP251XFD_REG_TSCON_TBCEN BIT(16)
153 #define MCP251XFD_REG_VEC_FILHIT_MASK GENMASK(12, 8)
159 #define MCP251XFD_REG_INT_IVMIE BIT(31)
160 #define MCP251XFD_REG_INT_WAKIE BIT(30)
161 #define MCP251XFD_REG_INT_CERRIE BIT(29)
162 #define MCP251XFD_REG_INT_SERRIE BIT(28)
163 #define MCP251XFD_REG_INT_RXOVIE BIT(27)
164 #define MCP251XFD_REG_INT_TXATIE BIT(26)
165 #define MCP251XFD_REG_INT_SPICRCIE BIT(25)
166 #define MCP251XFD_REG_INT_ECCIE BIT(24)
167 #define MCP251XFD_REG_INT_TEFIE BIT(20)
168 #define MCP251XFD_REG_INT_MODIE BIT(19)
169 #define MCP251XFD_REG_INT_TBCIE BIT(18)
170 #define MCP251XFD_REG_INT_RXIE BIT(17)
171 #define MCP251XFD_REG_INT_TXIE BIT(16)
172 #define MCP251XFD_REG_INT_IVMIF BIT(15)
173 #define MCP251XFD_REG_INT_WAKIF BIT(14)
174 #define MCP251XFD_REG_INT_CERRIF BIT(13)
175 #define MCP251XFD_REG_INT_SERRIF BIT(12)
176 #define MCP251XFD_REG_INT_RXOVIF BIT(11)
177 #define MCP251XFD_REG_INT_TXATIF BIT(10)
178 #define MCP251XFD_REG_INT_SPICRCIF BIT(9)
179 #define MCP251XFD_REG_INT_ECCIF BIT(8)
180 #define MCP251XFD_REG_INT_TEFIF BIT(4)
181 #define MCP251XFD_REG_INT_MODIF BIT(3)
182 #define MCP251XFD_REG_INT_TBCIF BIT(2)
183 #define MCP251XFD_REG_INT_RXIF BIT(1)
184 #define MCP251XFD_REG_INT_TXIF BIT(0)
198 #define MCP251XFD_REG_TREC_TXBO BIT(21)
199 #define MCP251XFD_REG_TREC_TXBP BIT(20)
200 #define MCP251XFD_REG_TREC_RXBP BIT(19)
201 #define MCP251XFD_REG_TREC_TXWARN BIT(18)
202 #define MCP251XFD_REG_TREC_RXWARN BIT(17)
203 #define MCP251XFD_REG_TREC_EWARN BIT(16)
204 #define MCP251XFD_REG_TREC_TEC_MASK GENMASK(15, 8)
210 #define MCP251XFD_REG_BDIAG0_NTERRCNT_MASK GENMASK(15, 8)
214 #define MCP251XFD_REG_BDIAG1_DLCMM BIT(31)
215 #define MCP251XFD_REG_BDIAG1_ESI BIT(30)
216 #define MCP251XFD_REG_BDIAG1_DCRCERR BIT(29)
217 #define MCP251XFD_REG_BDIAG1_DSTUFERR BIT(28)
218 #define MCP251XFD_REG_BDIAG1_DFORMERR BIT(27)
219 #define MCP251XFD_REG_BDIAG1_DBIT1ERR BIT(25)
220 #define MCP251XFD_REG_BDIAG1_DBIT0ERR BIT(24)
221 #define MCP251XFD_REG_BDIAG1_TXBOERR BIT(23)
222 #define MCP251XFD_REG_BDIAG1_NCRCERR BIT(21)
223 #define MCP251XFD_REG_BDIAG1_NSTUFERR BIT(20)
224 #define MCP251XFD_REG_BDIAG1_NFORMERR BIT(19)
225 #define MCP251XFD_REG_BDIAG1_NACKERR BIT(18)
226 #define MCP251XFD_REG_BDIAG1_NBIT1ERR BIT(17)
227 #define MCP251XFD_REG_BDIAG1_NBIT0ERR BIT(16)
240 #define MCP251XFD_REG_TEFCON_FRESET BIT(10)
241 #define MCP251XFD_REG_TEFCON_UINC BIT(8)
242 #define MCP251XFD_REG_TEFCON_TEFTSEN BIT(5)
243 #define MCP251XFD_REG_TEFCON_TEFOVIE BIT(3)
244 #define MCP251XFD_REG_TEFCON_TEFFIE BIT(2)
245 #define MCP251XFD_REG_TEFCON_TEFHIE BIT(1)
246 #define MCP251XFD_REG_TEFCON_TEFNEIE BIT(0)
249 #define MCP251XFD_REG_TEFSTA_TEFOVIF BIT(3)
250 #define MCP251XFD_REG_TEFSTA_TEFFIF BIT(2)
251 #define MCP251XFD_REG_TEFSTA_TEFHIF BIT(1)
252 #define MCP251XFD_REG_TEFSTA_TEFNEIF BIT(0)
272 #define MCP251XFD_REG_TXQCON_FRESET BIT(10)
273 #define MCP251XFD_REG_TXQCON_TXREQ BIT(9)
274 #define MCP251XFD_REG_TXQCON_UINC BIT(8)
275 #define MCP251XFD_REG_TXQCON_TXEN BIT(7)
276 #define MCP251XFD_REG_TXQCON_TXATIE BIT(4)
277 #define MCP251XFD_REG_TXQCON_TXQEIE BIT(2)
278 #define MCP251XFD_REG_TXQCON_TXQNIE BIT(0)
281 #define MCP251XFD_REG_TXQSTA_TXQCI_MASK GENMASK(12, 8)
282 #define MCP251XFD_REG_TXQSTA_TXABT BIT(7)
283 #define MCP251XFD_REG_TXQSTA_TXLARB BIT(6)
284 #define MCP251XFD_REG_TXQSTA_TXERR BIT(5)
285 #define MCP251XFD_REG_TXQSTA_TXATIF BIT(4)
286 #define MCP251XFD_REG_TXQSTA_TXQEIF BIT(2)
287 #define MCP251XFD_REG_TXQSTA_TXQNIF BIT(0)
307 #define MCP251XFD_REG_FIFOCON_FRESET BIT(10)
308 #define MCP251XFD_REG_FIFOCON_TXREQ BIT(9)
309 #define MCP251XFD_REG_FIFOCON_UINC BIT(8)
310 #define MCP251XFD_REG_FIFOCON_TXEN BIT(7)
311 #define MCP251XFD_REG_FIFOCON_RTREN BIT(6)
312 #define MCP251XFD_REG_FIFOCON_RXTSEN BIT(5)
313 #define MCP251XFD_REG_FIFOCON_TXATIE BIT(4)
314 #define MCP251XFD_REG_FIFOCON_RXOVIE BIT(3)
315 #define MCP251XFD_REG_FIFOCON_TFERFFIE BIT(2)
316 #define MCP251XFD_REG_FIFOCON_TFHRFHIE BIT(1)
317 #define MCP251XFD_REG_FIFOCON_TFNRFNIE BIT(0)
320 #define MCP251XFD_REG_FIFOSTA_FIFOCI_MASK GENMASK(12, 8)
321 #define MCP251XFD_REG_FIFOSTA_TXABT BIT(7)
322 #define MCP251XFD_REG_FIFOSTA_TXLARB BIT(6)
323 #define MCP251XFD_REG_FIFOSTA_TXERR BIT(5)
324 #define MCP251XFD_REG_FIFOSTA_TXATIF BIT(4)
325 #define MCP251XFD_REG_FIFOSTA_RXOVIF BIT(3)
326 #define MCP251XFD_REG_FIFOSTA_TFERFFIF BIT(2)
327 #define MCP251XFD_REG_FIFOSTA_TFHRFHIF BIT(1)
328 #define MCP251XFD_REG_FIFOSTA_TFNRFNIF BIT(0)
334 #define MCP251XFD_REG_BYTE_FLTCON_FLTEN BIT(7)
337 #define MCP251XFD_REG_FLTOBJ_EXIDE BIT(30)
338 #define MCP251XFD_REG_FLTOBJ_SID11 BIT(29)
343 #define MCP251XFD_REG_MASK_MIDE BIT(30)
344 #define MCP251XFD_REG_MASK_MSID11 BIT(29)
349 #define MCP251XFD_OBJ_ID_SID11 BIT(29)
355 #define MCP251XFD_OBJ_FLAGS_ESI BIT(8)
356 #define MCP251XFD_OBJ_FLAGS_FDF BIT(7)
357 #define MCP251XFD_OBJ_FLAGS_BRS BIT(6)
358 #define MCP251XFD_OBJ_FLAGS_RTR BIT(5)
359 #define MCP251XFD_OBJ_FLAGS_IDE BIT(4)
371 #define MCP251XFD_REG_OSC_SCLKRDY BIT(12)
372 #define MCP251XFD_REG_OSC_OSCRDY BIT(10)
373 #define MCP251XFD_REG_OSC_PLLRDY BIT(8)
379 #define MCP251XFD_REG_OSC_SCLKDIV BIT(4)
380 #define MCP251XFD_REG_OSC_LPMEN BIT(3) /* MCP2518FD only */
381 #define MCP251XFD_REG_OSC_OSCDIS BIT(2)
382 #define MCP251XFD_REG_OSC_PLLEN BIT(0)
385 #define MCP251XFD_REG_IOCON_INTOD BIT(30)
386 #define MCP251XFD_REG_IOCON_SOF BIT(29)
387 #define MCP251XFD_REG_IOCON_TXCANOD BIT(28)
388 #define MCP251XFD_REG_IOCON_PM1 BIT(25)
389 #define MCP251XFD_REG_IOCON_PM0 BIT(24)
390 #define MCP251XFD_REG_IOCON_GPIO1 BIT(17)
391 #define MCP251XFD_REG_IOCON_GPIO0 BIT(16)
392 #define MCP251XFD_REG_IOCON_LAT1 BIT(9)
393 #define MCP251XFD_REG_IOCON_LAT0 BIT(8)
394 #define MCP251XFD_REG_IOCON_XSTBYEN BIT(6)
395 #define MCP251XFD_REG_IOCON_TRIS1 BIT(1)
396 #define MCP251XFD_REG_IOCON_TRIS0 BIT(0)
399 #define MCP251XFD_REG_CRC_FERRIE BIT(25)
400 #define MCP251XFD_REG_CRC_CRCERRIE BIT(24)
401 #define MCP251XFD_REG_CRC_FERRIF BIT(17)
402 #define MCP251XFD_REG_CRC_CRCERRIF BIT(16)
407 #define MCP251XFD_REG_ECCCON_PARITY_MASK GENMASK(14, 8)
408 #define MCP251XFD_REG_ECCCON_DEDIE BIT(2)
409 #define MCP251XFD_REG_ECCCON_SECIE BIT(1)
410 #define MCP251XFD_REG_ECCCON_ECCEN BIT(0)
415 #define MCP251XFD_REG_ECCSTAT_DEDIF BIT(2)
416 #define MCP251XFD_REG_ECCSTAT_SECIF BIT(1)
467 uint8_t _unused[4 - (MCP251XFD_SPI_HEADER_LEN % 4)]; /* so that buf is 4-byte aligned */