Lines Matching full:adc
10 #include <zephyr/drivers/adc.h>
47 Adc *regs;
64 static void wait_synchronization(Adc *const adc) in wait_synchronization() argument
66 while ((ADC_SYNC(adc) & ADC_SYNC_MASK) != 0) { in wait_synchronization()
119 Adc *const adc = cfg->regs; in adc_sam0_channel_setup() local
127 LOG_ERR("Selected ADC acquisition time is not valid"); in adc_sam0_channel_setup()
134 adc->SAMPCTRL.reg = sampctrl; in adc_sam0_channel_setup()
135 wait_synchronization(adc); in adc_sam0_channel_setup()
165 if (adc->REFCTRL.reg != refctrl) { in adc_sam0_channel_setup()
167 adc->CTRLA.bit.ENABLE = 0; in adc_sam0_channel_setup()
168 wait_synchronization(adc); in adc_sam0_channel_setup()
170 adc->REFCTRL.reg = refctrl; in adc_sam0_channel_setup()
171 wait_synchronization(adc); in adc_sam0_channel_setup()
173 adc->CTRLA.bit.ENABLE = 1; in adc_sam0_channel_setup()
174 wait_synchronization(adc); in adc_sam0_channel_setup()
218 LOG_ERR("Selected ADC gain is not valid"); in adc_sam0_channel_setup()
226 ADC_DIFF(adc) |= ADC_DIFF_MASK; in adc_sam0_channel_setup()
230 ADC_DIFF(adc) &= ~ADC_DIFF_MASK; in adc_sam0_channel_setup()
232 wait_synchronization(adc); in adc_sam0_channel_setup()
234 adc->INPUTCTRL.reg = inputctrl; in adc_sam0_channel_setup()
235 wait_synchronization(adc); in adc_sam0_channel_setup()
268 Adc *const adc = cfg->regs; in adc_sam0_start_conversion() local
272 adc->SWTRIG.reg = ADC_SWTRIG_START; in adc_sam0_start_conversion()
275 * that might access the ADC after this will wait for it to complete in adc_sam0_start_conversion()
322 Adc *const adc = cfg->regs; in start_read() local
330 adc->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM(sequence->oversampling); in start_read()
339 adc->AVGCTRL.bit.ADJRES = sequence->oversampling - 4U; in start_read()
350 ADC_RESSEL(adc) = ADC_RESSEL_8BIT; in start_read()
358 ADC_RESSEL(adc) = ADC_RESSEL_10BIT; in start_read()
362 ADC_RESSEL(adc) = ADC_RESSEL_16BIT; in start_read()
364 ADC_RESSEL(adc) = ADC_RESSEL_12BIT; in start_read()
368 LOG_ERR("ADC resolution value %d is not valid", in start_read()
373 wait_synchronization(adc); in start_read()
424 Adc *const adc = cfg->regs; in adc_sam0_isr() local
427 adc->INTFLAG.reg = ADC_INTFLAG_MASK; in adc_sam0_isr()
429 result = (uint16_t)(adc->RESULT.reg); in adc_sam0_isr()
449 Adc *const adc = cfg->regs; in adc_sam0_init() local
467 ADC_PRESCALER(adc) = cfg->prescaler; in adc_sam0_init()
468 wait_synchronization(adc); in adc_sam0_init()
470 adc->INTENCLR.reg = ADC_INTENCLR_MASK; in adc_sam0_init()
471 adc->INTFLAG.reg = ADC_INTFLAG_MASK; in adc_sam0_init()
475 adc->INTENSET.reg = ADC_INTENSET_RESRDY; in adc_sam0_init()
482 adc->CTRLA.bit.ENABLE = 1; in adc_sam0_init()
483 wait_synchronization(adc); in adc_sam0_init()
528 Adc * const adc = cfg->regs; \
529 adc->CALIB.reg = ADC_SAM0_BIASCOMP(n) \
545 Adc * const adc = cfg->regs; \
555 adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | \
565 .regs = (Adc *)DT_INST_REG_ADDR(n), \