10 #include <zephyr/drivers/adc.h>
25 	Adc *regs;
70 	Adc *const adc = cfg->regs;  in adc_sam_channel_setup()  local
77 			LOG_ERR("Invalid ADC differential input for channel %u", channel_id);  in adc_sam_channel_setup()
82 			LOG_ERR("Invalid ADC single-ended input for channel %u", channel_id);  in adc_sam_channel_setup()
88 		LOG_ERR("Invalid ADC channel acquisition time");  in adc_sam_channel_setup()
93 		LOG_ERR("Invalid ADC channel reference (%d)", channel_cfg->reference);  in adc_sam_channel_setup()
99 		adc->ADC_ACR |= ADC_ACR_TSON;  in adc_sam_channel_setup()
104 		adc->ADC_COR |= (ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U);  in adc_sam_channel_setup()
106 		adc->ADC_COR &= ~((ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U));  in adc_sam_channel_setup()
110 	adc->ADC_CGR &= ~(ADC_CGR_GAIN0_Msk << (channel_id * 2U));  in adc_sam_channel_setup()
115 			LOG_ERR("ADC 1/2x gain only allowed for differential channel");  in adc_sam_channel_setup()
121 		adc->ADC_CGR |= ADC_CGR_GAIN0(1) << (channel_id * 2U);  in adc_sam_channel_setup()
124 		adc->ADC_CGR |= ADC_CGR_GAIN0(2) << (channel_id * 2U);  in adc_sam_channel_setup()
128 			LOG_ERR("ADC 4x gain only allowed for single-ended channel");  in adc_sam_channel_setup()
131 		adc->ADC_CGR |= ADC_CGR_GAIN0(3) << (channel_id * 2U);  in adc_sam_channel_setup()
134 		LOG_ERR("Invalid ADC channel gain (%d)", channel_cfg->gain);  in adc_sam_channel_setup()
144 	Adc *const adc = cfg->regs;  in adc_sam_start_conversion()  local
146 	adc->ADC_CR = ADC_CR_START;  in adc_sam_start_conversion()
157 	Adc *const adc = cfg->regs;  in adc_context_start_sampling()  local
162 	adc->ADC_CHDR = 0xffff;  in adc_context_start_sampling()
165 	adc->ADC_CHER = ctx->sequence.channels;  in adc_context_start_sampling()
221 		LOG_ERR("ADC resolution %d is not valid", sequence->resolution);  in start_read()
262 	Adc *const adc = cfg->regs;  in adc_sam_isr()  local
266 	if (adc->ADC_ISR & ADC_ISR_DRDY) {  in adc_sam_isr()
267 		result = adc->ADC_LCDR & ADC_LCDR_LDATA_Msk;  in adc_sam_isr()
285 	Adc *const adc = cfg->regs;  in adc_sam_init()  local
295 		LOG_ERR("Failed to get ADC peripheral clock rate (%d)", ret);  in adc_sam_init()
299 	/* Calculate ADC clock frequency */  in adc_sam_init()
302 		LOG_ERR("Invalid ADC clock frequency %d (1MHz < freq < 22Mhz)", frequency);  in adc_sam_init()
306 	/* The number of ADC pulses for conversion  */  in adc_sam_init()
312 	/* Reset ADC controller */  in adc_sam_init()
313 	adc->ADC_CR = ADC_CR_SWRST;  in adc_sam_init()
316 	adc->ADC_MR = 0U;  in adc_sam_init()
319 	adc->ADC_PTCR = ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS;  in adc_sam_init()
320 	adc->ADC_RCR = 0U;  in adc_sam_init()
321 	adc->ADC_RNCR = 0U;  in adc_sam_init()
324 	adc->ADC_MR = ADC_MR_PRESCAL(cfg->prescaler)  in adc_sam_init()
336 	adc->ADC_ACR = ADC_ACR_IBCTL(frequency < 500000U ? 0U : 1U);  in adc_sam_init()
338 	/* Enable ADC clock in PMC */  in adc_sam_init()
342 		LOG_ERR("Failed to enable ADC clock (%d)", ret);  in adc_sam_init()
354 	adc->ADC_IER = ADC_IER_DRDY;  in adc_sam_init()
398 		.regs = (Adc *)DT_INST_REG_ADDR(n),			\