Lines Matching full:arc
3 DesignWare ARC nSIM and HAPS FPGA boards
9 This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in
10 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
13 * ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to
14 :ref:`here <hardware_arch_arc_support_status>` for a complete list of ARC processor families which
18 ARC processors are known for being highly customizable and some but not all of the configurations
19 are currently supported in the Zephyr RTOS for ARC, again please refer to
25 * ``nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
27 * ``nsim_em_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
28 * ``nsim_em_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and
30 * ``nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
42 ``.props`` or ``.args`` files in :zephyr_file:`boards/arc/nsim/support/` directory to understand
58 :zephyr_file:`boards/arc/nsim/support/nsim_hs5x.props` and
59 :zephyr_file:`boards/arc/nsim/support/mdb_hs5x.args`.
65 :zephyr_file:`boards/arc/nsim/support/mdb_hs5x_smp.args`.
78 either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required.
81 `DesignWare ARC nSIM`_ and MetaWare Debugger from `ARC MWDT`_ are required.
84 MetaWare Debugger from `ARC MWDT`_ is required as well as the HAPS platform itself.
89 Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however
93 I.e. for the ``nsim_hs5x`` board we can check :zephyr_file:`boards/arc/nsim/nsim_hs5x.yaml`
97 * **zephyr** - implies ARC GNU toolchain from Zephyr SDK. You can find more information about
99 * **cross-compile** - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that
103 * **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its
165 * Supports wider range of ARC hardware features
199 …ons -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs…
200 …ons -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs…
208 …ons -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs…
209 …ons -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs…
225 ARC cores which don't share any memory regions with each other and so SMP-enabled code won't
235 It's the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC
253 west debugserver --runner arc-nsim
255 In terminal two, connect to the GDB server using ARC GDB. You can find it in Zephyr SDK:
257 * for the ARCv2 targets you should use :file:`arc-zephyr-elf-gdb`
265 arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf
298 Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific
319 it is :zephyr_file:`soc/arc/snps_nsim/CMakeLists.txt`.
336 .. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim
337 .. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi