Lines Matching +full:feature +full:- +full:specific

1 # Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
13 	bool "Hard-float calling convention"
17 	  This option enables the hard-float calling convention.
20 	bool "RISC-V global pointer relative addressing"
27 	  Note: To support this feature, RISC-V SoC needs to initialize
37 	  This is for RISC-V implementations that require every mret to be
38 	  balanced with an ecall. This is not required by the RISC-V spec
54 	  Enable low-level SOC-specific hardware stacking / unstacking
56 	  if this feature is supported.
66 	  - SOC_ISR_SW_STACKING: macro guarded by _ASMLANGUAGE called by the
71 	  - SOC_ISR_SW_UNSTACKING: macro guarded by _ASMLANGUAGE called by the
75 	  - SOC_ISR_STACKING_ESF_DECLARE: structure declaration for the ESF
86 	  platform-specific versions named z_soc_irq_lock(), z_soc_irq_unlock()
90 	  the RISC-V SoC needs to do something different and more than reading and
97 	  platform-specific versions named z_soc_sys_read*() and z_soc_sys_write*().
100 	  the RISC-V SoC needs to do something different and more than reading and
104 	bool "SOC-based context saving in IRQ handlers"
107 	  Enable low-level SOC-specific context management, for SOCs
115 	  - SOC_ESF_MEMBERS: structure component declarations to
117 	    end in a semicolon, for portability. The generic RISC-V
122 	  - SOC_ESF_INIT: structure contents initializer for struct soc_esf
139 	bool "SOC-based offsets"
144 	  - GEN_SOC_OFFSET_SYMS(): a macro which expands to
151 	bool "SOC-based interrupt initialization"
153 	  Enable SOC-based interrupt initialization
188 	  intended for inter-hart interrupt signaling and so retained for that
203 	  For RISC-V systems such as MPFS and FU540 this would be set to 1 to
207 	bool "RISC-V PMP Support"
237 	  Set this if NA4 (Naturally Aligned 4-byte) mode is not supported.
245 	bool "Enforce power-of-two alignment on PMP memory areas" if !PMP_NO_TOR
327 	int "Alignment of RISC-V trap handler in bytes"
330 	  This value configures the alignment of RISC-V trap handling
332 	  the format of MTVEC register which is RISC-V platform-specific.