Lines Matching +full:non +full:- +full:interrupt

3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
22 	  non-GIC) interrupt controller.
24 	  A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
25 	  allow interfacing to a custom external interrupt controller and this
26 	  option must be selected when such cores are connected to an interrupt
27 	  controller that is not the ARM Generic Interrupt Controller (GIC).
29 	  When this option is selected, the architecture interrupt control
30 	  functions are mapped to the SoC interrupt control interface, which is
33 	  N.B. This option is only applicable to the Cortex-A and Cortex-R
34 	       family cores. The Cortex-M family cores are always equipped with
35 	       the ARM Nested Vectored Interrupt Controller (NVIC).
69 	  Enables a possibility to inject SoC-specific code just after WFI/WFE