93 	IPCC_TypeDef *ipcc;  member
112 	mask = (~IPCC_ReadReg(cfg->ipcc, MR)) & IPCC_ALL_MR_RXO_CH_MASK;  in stm32_ipcc_mailbox_rx_isr()
113 	mask &= IPCC_ReadOtherInstReg_SR(cfg->ipcc) & IPCC_ALL_SR_CH_MASK;  in stm32_ipcc_mailbox_rx_isr()
121 		IPCC_DisableReceiveChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_rx_isr()
128 		IPCC_ClearFlag_CHx(cfg->ipcc, i);  in stm32_ipcc_mailbox_rx_isr()
129 		IPCC_EnableReceiveChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_rx_isr()
139 	mask = (~IPCC_ReadReg(cfg->ipcc, MR)) & IPCC_ALL_MR_TXF_CH_MASK;  in stm32_ipcc_mailbox_tx_isr()
142 	mask &= IPCC_ReadReg_SR(cfg->ipcc) & IPCC_ALL_SR_CH_MASK;  in stm32_ipcc_mailbox_tx_isr()
150 		IPCC_DisableTransmitChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_tx_isr()
177 	if (IPCC_IsActiveFlag_CHx(cfg->ipcc, id)) {  in stm32_ipcc_mailbox_ipm_send()
179 		while (IPCC_IsActiveFlag_CHx(cfg->ipcc, id)) {  in stm32_ipcc_mailbox_ipm_send()
183 	IPCC_EnableTransmitChannel(cfg->ipcc, id);  in stm32_ipcc_mailbox_ipm_send()
184 	IPCC_SetFlag_CHx(cfg->ipcc, id);  in stm32_ipcc_mailbox_ipm_send()
225 		IPCC_EnableIT_TXF(cfg->ipcc);  in stm32_ipcc_mailbox_ipm_set_enabled()
226 		IPCC_EnableIT_RXO(cfg->ipcc);  in stm32_ipcc_mailbox_ipm_set_enabled()
228 			IPCC_EnableReceiveChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_ipm_set_enabled()
232 		IPCC_DisableIT_TXF(cfg->ipcc);  in stm32_ipcc_mailbox_ipm_set_enabled()
233 		IPCC_DisableIT_RXO(cfg->ipcc);  in stm32_ipcc_mailbox_ipm_set_enabled()
235 			IPCC_DisableReceiveChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_ipm_set_enabled()
259 	IPCC_DisableIT_TXF(cfg->ipcc);  in stm32_ipcc_mailbox_init()
260 	IPCC_DisableIT_RXO(cfg->ipcc);  in stm32_ipcc_mailbox_init()
262 	data->num_ch = LL_IPCC_GetChannelConfig(cfg->ipcc);  in stm32_ipcc_mailbox_init()
266 		IPCC_ClearFlag_CHx(cfg->ipcc, i);  in stm32_ipcc_mailbox_init()
268 		IPCC_DisableReceiveChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_init()
269 		IPCC_DisableTransmitChannel(cfg->ipcc, i);  in stm32_ipcc_mailbox_init()
290 	.ipcc = (IPCC_TypeDef *)DT_INST_REG_ADDR(0),