84 static void pcie_generic_ctrl_enumerate_bars(const struct device *ctrl_dev, pcie_bdf_t bdf,  in pcie_generic_ctrl_enumerate_bars()  argument
95 		data = scratch = pcie_ctrl_conf_read(ctrl_dev, bdf, reg);  in pcie_generic_ctrl_enumerate_bars()
105 				scratch |= ((uint64_t)pcie_ctrl_conf_read(ctrl_dev, bdf, reg + 1))  in pcie_generic_ctrl_enumerate_bars()
117 		pcie_ctrl_conf_write(ctrl_dev, bdf, reg, 0xFFFFFFFF);  in pcie_generic_ctrl_enumerate_bars()
118 		size = pcie_ctrl_conf_read(ctrl_dev, bdf, reg);  in pcie_generic_ctrl_enumerate_bars()
119 		pcie_ctrl_conf_write(ctrl_dev, bdf, reg, scratch & 0xFFFFFFFF);  in pcie_generic_ctrl_enumerate_bars()
122 			pcie_ctrl_conf_write(ctrl_dev, bdf, reg + 1, 0xFFFFFFFF);  in pcie_generic_ctrl_enumerate_bars()
123 			size |= ((uint64_t)pcie_ctrl_conf_read(ctrl_dev, bdf, reg + 1)) << 32;  in pcie_generic_ctrl_enumerate_bars()
124 			pcie_ctrl_conf_write(ctrl_dev, bdf, reg + 1, scratch >> 32);  in pcie_generic_ctrl_enumerate_bars()
144 		if (pcie_ctrl_region_allocate(ctrl_dev, bdf, found_mem,  in pcie_generic_ctrl_enumerate_bars()
148 			pcie_ctrl_region_translate(ctrl_dev, bdf, found_mem,  in pcie_generic_ctrl_enumerate_bars()
159 			pcie_ctrl_conf_write(ctrl_dev, bdf, reg, bar_bus_addr & 0xFFFFFFFF);  in pcie_generic_ctrl_enumerate_bars()
161 				pcie_ctrl_conf_write(ctrl_dev, bdf, reg + 1, bar_bus_addr >> 32);  in pcie_generic_ctrl_enumerate_bars()
175 static bool pcie_generic_ctrl_enumerate_type1(const struct device *ctrl_dev, pcie_bdf_t bdf,  in pcie_generic_ctrl_enumerate_type1()  argument
178 	uint32_t class = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_CONF_CLASSREV);  in pcie_generic_ctrl_enumerate_type1()
183 		uint32_t number = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_BUS_NUMBER);  in pcie_generic_ctrl_enumerate_type1()
186 		pcie_generic_ctrl_enumerate_bars(ctrl_dev, bdf, 2);  in pcie_generic_ctrl_enumerate_type1()
190 			ctrl_dev, bdf, PCIE_BUS_NUMBER,  in pcie_generic_ctrl_enumerate_type1()
196 		if (pcie_ctrl_region_get_allocate_base(ctrl_dev, bdf, false, false,  in pcie_generic_ctrl_enumerate_type1()
198 			uint32_t io = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_IO_SEC_STATUS);  in pcie_generic_ctrl_enumerate_type1()
200 				pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_IO_BASE_LIMIT_UPPER);  in pcie_generic_ctrl_enumerate_type1()
202 			pcie_ctrl_conf_write(ctrl_dev, bdf, PCIE_IO_SEC_STATUS,  in pcie_generic_ctrl_enumerate_type1()
208 				ctrl_dev, bdf, PCIE_IO_BASE_LIMIT_UPPER,  in pcie_generic_ctrl_enumerate_type1()
212 			pcie_ctrl_set_cmd(ctrl_dev, bdf, PCIE_CONF_CMDSTAT_IO, true);  in pcie_generic_ctrl_enumerate_type1()
216 		if (pcie_ctrl_region_get_allocate_base(ctrl_dev, bdf, true, false,  in pcie_generic_ctrl_enumerate_type1()
218 			uint32_t mem = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_MEM_BASE_LIMIT);  in pcie_generic_ctrl_enumerate_type1()
221 				ctrl_dev, bdf, PCIE_MEM_BASE_LIMIT,  in pcie_generic_ctrl_enumerate_type1()
225 			pcie_ctrl_set_cmd(ctrl_dev, bdf, PCIE_CONF_CMDSTAT_MEM, true);  in pcie_generic_ctrl_enumerate_type1()
230 		pcie_ctrl_set_cmd(ctrl_dev, bdf, PCIE_CONF_CMDSTAT_MASTER, true);  in pcie_generic_ctrl_enumerate_type1()
238 static void pcie_generic_ctrl_post_enumerate_type1(const struct device *ctrl_dev, pcie_bdf_t bdf,  in pcie_generic_ctrl_post_enumerate_type1()  argument
241 	uint32_t number = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_BUS_NUMBER);  in pcie_generic_ctrl_post_enumerate_type1()
245 	pcie_ctrl_conf_write(ctrl_dev, bdf, PCIE_BUS_NUMBER,  in pcie_generic_ctrl_post_enumerate_type1()
252 	if (pcie_ctrl_region_get_allocate_base(ctrl_dev, bdf, false, false,  in pcie_generic_ctrl_post_enumerate_type1()
254 		uint32_t io = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_IO_SEC_STATUS);  in pcie_generic_ctrl_post_enumerate_type1()
255 		uint32_t io_upper = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_IO_BASE_LIMIT_UPPER);  in pcie_generic_ctrl_post_enumerate_type1()
258 			ctrl_dev, bdf, PCIE_IO_SEC_STATUS,  in pcie_generic_ctrl_post_enumerate_type1()
264 			ctrl_dev, bdf, PCIE_IO_BASE_LIMIT_UPPER,  in pcie_generic_ctrl_post_enumerate_type1()
270 	if (pcie_ctrl_region_get_allocate_base(ctrl_dev, bdf, true, false,  in pcie_generic_ctrl_post_enumerate_type1()
272 		uint32_t mem = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_MEM_BASE_LIMIT);  in pcie_generic_ctrl_post_enumerate_type1()
275 			ctrl_dev, bdf, PCIE_MEM_BASE_LIMIT,  in pcie_generic_ctrl_post_enumerate_type1()
282 static void pcie_generic_ctrl_enumerate_type0(const struct device *ctrl_dev, pcie_bdf_t bdf)  in pcie_generic_ctrl_enumerate_type0()  argument
285 	pcie_generic_ctrl_enumerate_bars(ctrl_dev, bdf, 6);  in pcie_generic_ctrl_enumerate_type0()
288 static bool pcie_generic_ctrl_enumerate_endpoint(const struct device *ctrl_dev,  in pcie_generic_ctrl_enumerate_endpoint()  argument
299 	id = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_CONF_ID);  in pcie_generic_ctrl_enumerate_endpoint()
304 	class = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_CONF_CLASSREV);  in pcie_generic_ctrl_enumerate_endpoint()
305 	data = pcie_ctrl_conf_read(ctrl_dev, bdf, PCIE_CONF_TYPE);  in pcie_generic_ctrl_enumerate_endpoint()
327 		is_bridge = pcie_generic_ctrl_enumerate_type1(ctrl_dev, bdf, bus_number);  in pcie_generic_ctrl_enumerate_endpoint()
329 		pcie_generic_ctrl_enumerate_type0(ctrl_dev, bdf);  in pcie_generic_ctrl_enumerate_endpoint()
369 void pcie_generic_ctrl_enumerate(const struct device *ctrl_dev, pcie_bdf_t bdf_start)  in pcie_generic_ctrl_enumerate()  argument
389 			pcie_generic_ctrl_post_enumerate_type1(ctrl_dev, state->bridge_bdf,  in pcie_generic_ctrl_enumerate()
398 				is_bridge = pcie_generic_ctrl_enumerate_endpoint(ctrl_dev,  in pcie_generic_ctrl_enumerate()