Lines Matching refs:val
68 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG) argument
69 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG) argument
70 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG) argument
71 #define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR1_REG) argument
72 #define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR1_REG) argument
73 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG) argument
74 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG) argument
75 #define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG) argument
76 #define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG) argument
77 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) argument
78 #define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) argument
79 #define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG) argument
80 #define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR1_REG) argument
81 #define ICKLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG) argument
82 #define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG) argument
84 #define MDF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG) argument
85 #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) argument
86 #define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) argument
87 #define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG) argument
88 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) argument
89 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG) argument
90 #define DSIHOST_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR2_REG) argument
91 #define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR2_REG) argument
92 #define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CCIPR2_REG) argument
93 #define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) argument
94 #define HSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR2_REG) argument
95 #define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR2_REG) argument
96 #define I2C6_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR2_REG) argument
97 #define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR2_REG) argument
99 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG) argument
100 #define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG) argument
101 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG) argument
102 #define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG) argument
103 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG) argument
104 #define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG) argument
105 #define DAC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR3_REG) argument
106 #define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR3_REG) argument
108 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) argument
111 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) argument
112 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) argument