67 #define REG_PWR_MGMT0_ACCEL_MODE(val)			((val) & BIT_MASK(2))  argument
68 #define REG_PWR_MGMT0_GYRO_MODE(val)			(((val) & BIT_MASK(2)) << 2)  argument
70 #define REG_ACCEL_CONFIG0_ODR(val)			((val) & BIT_MASK(4))  argument
71 #define REG_ACCEL_CONFIG0_FS(val)			(((val) & BIT_MASK(3)) << 4)  argument
73 #define REG_GYRO_CONFIG0_ODR(val)			((val) & BIT_MASK(4))  argument
74 #define REG_GYRO_CONFIG0_FS(val)			(((val) & BIT_MASK(4)) << 4)  argument
76 #define REG_DRIVE_CONFIG0_SPI_SLEW(val)			(((val) & BIT_MASK(2)) << 1)  argument
78 #define REG_MISC2_SOFT_RST(val)				((val << 1) & BIT(1))  argument
80 #define REG_IPREG_SYS1_REG_172_GYRO_LPFBW_SEL(val)	(val & BIT_MASK(3))  argument
82 #define REG_IPREG_SYS2_REG_131_ACCEL_LPFBW_SEL(val)	(val & BIT_MASK(3))  argument
84 #define REG_INT1_CONFIG0_STATUS_EN_DRDY(val)		(((val) & BIT_MASK(1)) << 2)  argument
85 #define REG_INT1_CONFIG0_STATUS_EN_FIFO_THS(val)	(((val) & BIT_MASK(1)) << 1)  argument
86 #define REG_INT1_CONFIG0_STATUS_EN_FIFO_FULL(val)	((val) & BIT_MASK(1))  argument
88 #define REG_INT1_CONFIG2_EN_OPEN_DRAIN(val)		(((val) & BIT_MASK(1)) << 2)  argument
89 #define REG_INT1_CONFIG2_EN_LATCH_MODE(val)		(((val) & BIT_MASK(1)) << 1)  argument
90 #define REG_INT1_CONFIG2_EN_ACTIVE_HIGH(val)		((val) & BIT_MASK(1))  argument
92 #define REG_INT1_STATUS0_DRDY(val)			(((val) & BIT_MASK(1)) << 2)  argument
93 #define REG_INT1_STATUS0_FIFO_THS(val)			(((val) & BIT_MASK(1)) << 1)  argument
94 #define REG_INT1_STATUS0_FIFO_FULL(val)			((val) & BIT_MASK(1))  argument
103 #define REG_FIFO_CONFIG0_FIFO_MODE(val)			(((val) & BIT_MASK(2)) << 6)  argument
104 #define REG_FIFO_CONFIG0_FIFO_DEPTH(val)		((val) & BIT_MASK(6))  argument
106 #define REG_FIFO_CONFIG1_0_FIFO_WM_THS(val)		((val) & BIT_MASK(8))  argument
107 #define REG_FIFO_CONFIG1_1_FIFO_WM_THS(val)		(((val) >> 8) & BIT_MASK(8))  argument
109 #define REG_FIFO_CONFIG2_FIFO_FLUSH(val)		(((val) & BIT_MASK(1)) << 7)  argument
110 #define REG_FIFO_CONFIG2_FIFO_WM_GT_THS(val)		(((val) & BIT_MASK(1)) << 3)  argument
112 #define REG_FIFO_CONFIG3_FIFO_HIRES_EN(val)		(((val) & BIT_MASK(1)) << 3)  argument
113 #define REG_FIFO_CONFIG3_FIFO_GYRO_EN(val)		(((val) & BIT_MASK(1)) << 2)  argument
114 #define REG_FIFO_CONFIG3_FIFO_ACCEL_EN(val)		(((val) & BIT_MASK(1)) << 1)  argument
115 #define REG_FIFO_CONFIG3_FIFO_EN(val)			((val) & BIT_MASK(1))  argument
120 #define REG_IREG_PREPARE_WRITE_ARRAY(base, reg, val)	{((base) >> 8) & 0xFF, reg, val}  argument
122 #define FIFO_HEADER_EXT_HEADER_EN(val)			(((val) & BIT_MASK(1)) << 7)  argument
123 #define FIFO_HEADER_ACCEL_EN(val)			(((val) & BIT_MASK(1)) << 6)  argument
124 #define FIFO_HEADER_GYRO_EN(val)			(((val) & BIT_MASK(1)) << 5)  argument
125 #define FIFO_HEADER_HIRES_EN(val)			(((val) & BIT_MASK(1)) << 4)  argument