206 static void pcr_slp_init(struct pcr_hw_regs *pcr)  in pcr_slp_init()  argument
208 	pcr->SYS_SLP_CTRL = 0U;  in pcr_slp_init()
212 		pcr->SLP_EN[i] = 0U;  in pcr_slp_init()
215 	pcr->SLP_EN[3] = XEC_CC_PCR3_CRYPTO_MASK;  in pcr_slp_init()
233 static int pll_wait_lock_periph(struct pcr_hw_regs *const pcr, uint16_t ms)  in pll_wait_lock_periph()  argument
244 	while (!(pcr->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK)) {  in pll_wait_lock_periph()
281 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in soc_clk32_init()  local
314 	rc = pll_wait_lock_periph(pcr, devcfg->xtal_enable_delay_ms);  in soc_clk32_init()
361 static uint32_t spin_delay(struct pcr_hw_regs *pcr, uint32_t cnt)  in spin_delay()  argument
366 		pcr->OSC_ID = n;  in spin_delay()
378 static int pll_wait_lock(struct pcr_hw_regs *const pcr, uint32_t wait_cnt)  in pll_wait_lock()  argument
380 	while (!(pcr->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK)) {  in pll_wait_lock()
493 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in check_32k_crystal()  local
503 	pcr->CNT32K_CTRL = 0U;  in check_32k_crystal()
504 	pcr->CLK32K_MON_IEN = 0U;  in check_32k_crystal()
505 	pcr->CLK32K_MON_ISTS = MCHP_PCR_CLK32M_ISTS_MASK;  in check_32k_crystal()
507 	pcr->CNT32K_PER_MIN = devcfg->period_min;  in check_32k_crystal()
508 	pcr->CNT32K_PER_MAX = devcfg->period_max;  in check_32k_crystal()
509 	pcr->CNT32K_DV_MAX = devcfg->max_dc_va;  in check_32k_crystal()
510 	pcr->CNT32K_VALID_MIN = devcfg->min_valid;  in check_32k_crystal()
512 	pcr->CNT32K_CTRL =  in check_32k_crystal()
518 	status = pcr->CLK32K_MON_ISTS;  in check_32k_crystal()
535 		status = pcr->CLK32K_MON_ISTS;  in check_32k_crystal()
538 	pcr->CNT32K_CTRL = 0u;  in check_32k_crystal()
564 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in connect_pll_32k()  local
579 	pcr->CLK32K_SRC_VTR = pcr_clk_sel;  in connect_pll_32k()
610 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in get_pll_32k_source()  local
613 	switch (pcr->CLK32K_SRC_VTR & XEC_CC_PCR_CLK32K_SRC_MSK) {  in get_pll_32k_source()
673 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in soc_clk32_init()  local
678 	pcr->CNT32K_CTRL = MCHP_PCR_CLK32M_CTRL_CLR_CNT;  in soc_clk32_init()
679 	pcr->CLK32K_MON_ISTS = MCHP_PCR_CLK32M_ISTS_MASK;  in soc_clk32_init()
680 	pcr->CLK32K_MON_IEN = 0;  in soc_clk32_init()
684 		spin_delay(pcr, CLK32K_SIL_OSC_DELAY);  in soc_clk32_init()
691 	rc = pll_wait_lock(pcr, CLK32K_PLL_LOCK_WAIT);  in soc_clk32_init()
718 		rc = pll_wait_lock_periph(pcr, devcfg->pll_lock_timeout_ms);  in soc_clk32_init()
758 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0);  in xec_clock_control_core_clock_divider_set()  local
764 	pcr->PROC_CLK_CTRL = (uint32_t)clkdiv;  in xec_clock_control_core_clock_divider_set()
783 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0);  in z_mchp_xec_pcr_periph_sleep()  local
790 		pcr->SLP_EN[slp_idx] |= BIT(slp_pos);  in z_mchp_xec_pcr_periph_sleep()
792 		pcr->SLP_EN[slp_idx] &= ~BIT(slp_pos);  in z_mchp_xec_pcr_periph_sleep()
804 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0);  in z_mchp_xec_pcr_periph_reset()  local
812 	pcr->RST_EN_LOCK = XEC_CC_PCR_RST_EN_UNLOCK;  in z_mchp_xec_pcr_periph_reset()
813 	pcr->RST_EN[slp_idx] = BIT(slp_pos);  in z_mchp_xec_pcr_periph_reset()
814 	pcr->RST_EN_LOCK = XEC_CC_PCR_RST_EN_LOCK;  in z_mchp_xec_pcr_periph_reset()
827 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0);  in xec_cc_on()  local
862 			pcr->SLP_EN[pcr_idx] &= ~BIT(bitpos);  in xec_cc_on()
864 			pcr->SLP_EN[pcr_idx] |= BIT(bitpos);  in xec_cc_on()
869 			pcr->SLOW_CLK_CTRL =  in xec_cc_on()
872 			pcr->SLOW_CLK_CTRL = 0;  in xec_cc_on()
924 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in get_turbo_clock()
926 	if (pcr->TURBO_CLK & XEC_CC_PCR_TURBO_CLK_96M) {  in get_turbo_clock()
959 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in xec_clock_control_get_subsys_rate()  local
972 		*rate = turbo_clock / pcr->PROC_CLK_CTRL;  in xec_clock_control_get_subsys_rate()
979 		temp = pcr->SLOW_CLK_CTRL;  in xec_clock_control_get_subsys_rate()
997 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0);  in mchp_xec_clk_ctrl_sys_sleep_enable()  local
1005 	pcr->SYS_SLP_CTRL = sys_sleep_mode;  in mchp_xec_clk_ctrl_sys_sleep_enable()
1010 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0);  in mchp_xec_clk_ctrl_sys_sleep_disable()  local
1011 	pcr->SYS_SLP_CTRL = 0;  in mchp_xec_clk_ctrl_sys_sleep_disable()
1026 	struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base;  in xec_clock_control_init()  local
1036 	pcr_slp_init(pcr);  in xec_clock_control_init()