readme_threadx.txt
1 Microsoft's Azure RTOS ThreadX for Renesas RXv3
2
3 Using the GNU Tools
4
5
61. Building the ThreadX run-time Library
7
8Please see the Samples repository on GitHub for the Azure RTOS demonstrations
9for the RXv3.
10
11
122. Demonstration System
13
14
15Please see the Samples repository on GitHub for the Azure RTOS demonstrations
16for the RXv3.
17
18
193. System Initialization
20
21The system entry point using the GNU tools is at the label _PowerON_Reset.
22
23The vector area is setup in the file tx_initialize_low_level.S. This file is also
24responsible for setting up various system data structures, interrupt vectors, and
25the periodic timer interrupt. This file is also an ideal place to add additional hardware
26initialization code.
27
28The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt
29source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the
30interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in
31r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer
32parameters as needed. Increasing the timer interrupt frequency increases the overhead
33of the timer handling code on the system.
34
35In addition, _tx_initialize_low_level determines the first available address for use
36by the application, which is supplied as the sole input parameter to your application
37definition function, tx_application_define. The first available memory is determined
38by the location of the '_end' label the is defined in the linker script.
39'_end' should reference the first memory AFTER all other RAM
40sections in your linker control file.
41
42
434. Context Switch, Register Usage and Stack Frames
44
45The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27,
46to perform context switch with the interrupt priority level 1. This ISR is thus reserved
47when using ThreadX and the SWINT should not be manipulated in any way by the application.
48The port will setup the interrupt within _tx_initialize_low_level and the compiler will
49automatically install the necessary interrupt vector. As such no additional initialization
50is necessary by the application.
51
52The following defines the saved context stack frame used by the ThreadX port. The
53state of the CPU registers at the time of a context switch is saved on the running
54thread's stack The top of the suspended thread's stack is pointed to by
55tx_thread_stack_ptr in the associated thread control block TX_THREAD.
56
57 Offset Stack Frame without DFPU Register
58
59 0x00 ACC0
60 0x04 ACC1
61 0x08 R6
62 0x0C R7
63 0x10 R8
64 0x14 R9
65 0x18 R10
66 0x1C R11
67 0x20 R12
68 0x24 R13
69 0x28 FPSW
70 0x2C R14
71 0x30 R15
72 0x34 R3
73 0x38 R4
74 0x3C R5
75 0x40 R1
76 0x44 R2
77 0x48 PC - return address
78 0x4C PSW
79
80 Offset Stack Frame with DFPU Register
81
82 0x00 DPSW
83 0x04 DCMR
84 0x08 DECNT
85 0x0C DEPC
86 0x10 DR0
87 0x14 DR1
88 0x18 DR2
89 0x1C DR3
90 0x20 DR4
91 0x24 DR5
92 0x28 DR6
93 0x2C DR7
94 0x30 DR8
95 0x34 DR9
96 0x38 DR10
97 0x3C DR11
98 0x40 DR12
99 0x44 DR13
100 0x48 DR14
101 0x4C DR15
102 0x50 ACC0
103 0x54 ACC1
104 0x58 R6
105 0x5C R7
106 0x60 R8
107 0x64 R9
108 0x68 R10
109 0x6C R11
110 0x70 R12
111 0x74 R13
112 0x78 FPSW
113 0x7C R14
114 0x80 R15
115 0x84 R3
116 0x88 R4
117 0x8C R5
118 0x90 R1
119 0x94 R2
120 0x98 PC - return address
121 0x9C PSW
122
123Note: By default GNURX does not save the state of the accumulator registers ACC0 and ACC1
124when entering an ISR. This means that if the ISR uses any of the DSP instructions the
125content of those registers could be corrupted. Saving and restoring of the accumulators
126can be enabled by adding the -msave-acc-in-interrupts command line option.
127
1285. Double Precision FPU Instructions Support
129
130The RXv3 architecture supports an optional set of double precision instructions which
131makes use of a new set of registers that must be saved and restored during context
132switches. This feature can be accessed by adding the -mdfpu -m64bit-doubles compiler switches.
133To reduce the overhead of saving and restoring the FPU registers for all threads
134the RXv3 port allows each thread to enable and disable saving and restoring the DFPU
135registers. By default the feature is disabled for new threads. To enable the feature
136tx_thread_fpu_enable() must be called within the context of every thread that will
137perform FPU operation. The saving and restoring of DFPU registers can be disabled
138again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes
139occasional use of the FPU.
140
1416. Improving Performance
142
143The distribution version of ThreadX is built without any compiler optimizations. This
144makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself.
145Of course, this costs some performance. To make ThreadX run faster, you can change the
146ThreadX Library project to disable debug information and enable the desired optimizations.
147
148In addition, you can eliminate the ThreadX basic API error checking by compiling your
149application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h
150is included.
151
152
1537. Timer Processing
154
155Timer processing is performed by calling __tx_timer_interrupt(). This should usually be done
156from within the callback of a periodic timer with a period of 100Hz. In the sample projects,
157a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source.
158
159
1608. Interrupt Handling
161
162Interrupt handling is unaffected by the ThreadX port as such user interrupts can be
163written according to the toolchain's documentation. It is recommended not to use interrupt
164priority 1 as this is the priority of the context switch interrupt. However using interrupt
165priority 1 won't cause any negative side effects but doing so may slightly reduce
166performance. Please refer to the toolchain documentation for additional details on how to
167define interrupt service routines.
168
169
1709. Execution Profiling
171
172The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists
173of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation
174of the EPK for generic usage details.
175
176To add the EPK to your RXv3 release make the following modifications:
177
178* Enable the following define for both the Threadx library and the application
179TX_EXECUTION_PROFILE_ENABLE
180
181* Setup CMT1 as a free running 16 bit timer.
182
183* In tx_execution_profile.h, change following around line 52:
184
185#ifdef TX_EXECUTION_64BIT_TIME
186typedef unsigned long long EXECUTION_TIME;
187#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFFFFFFFFFFFFFF
188#else
189typedef unsigned long EXECUTION_TIME;
190#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF
191#endif
192
193/* Define basic constants for the execution profile kit. */
194
195#define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A)
196
197Rebuild the Threadx library and the application.
198Refer to the EPK documentation how to interpret the results.
199
200
20110. Revision History
202
203For generic code revision information, please refer to the readme_threadx_generic.txt
204file, which is included in your distribution. The following details the revision
205information associated with this specific port of ThreadX:
206
20704-25-2022 Release 6.1.11 changes:
208 tx_thread_schedule.s Added low power support
209
21001-31-2022 Release 6.1.10 changes:
211 tx_port.h Added missing interrupt control defines
212 tx_timer_interrupt.s Added missing thread preemption logic
213
21410-15-2021 Release 6.1.9 changes:
215 tx_port.h Added FPU support
216 tx_thread_context_restore.s Added FPU support
217 tx_thread_schedule.s Added FPU support
218 tx_thread_system_return.s Added FPU support
219
22006-02-2021 Initial ThreadX release for the RXv3 using GNURX tools, version 6.1.7
221
222
223Copyright(c) 1996-2022 Microsoft Corporation
224
225
226https://azure.com/rtos
227
228
