readme_threadx.txt
1 Microsoft's Azure RTOS ThreadX for Cortex-M4
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3 Thumb & 32-bit Mode
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5 Using the Keil Microcontroller Development Kit
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71. Building the ThreadX run-time Library
8
9Building the ThreadX library is easy, simply load the project file
10ThreadX_Library.Uv2, which is located inside the "example_build" directory.
11
12Once the ThreadX library files are displayed in the project window,
13select the "Build Target" operation and observe the compilation and assembly
14of the ThreadX library. This project build produces the ThreadX library
15file ThreadX_Library.lib.
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17
182. Demonstration System
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20The ThreadX demonstration is designed to execute under the Keil debugger or
21Cortex-M4 hardware. This demonstration is slightly smaller than typical ThreadX
22demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM.
23
24Building the demonstration is easy; simply open the ThreadX demonstration
25project file ThreadX_Demo.Uv2, which is located inside the "example_build"
26directory.
27
28Once open, select the "Build Target" operation and observe the compilation of
29sample_threadx.c (which is the demonstration application) and linking with
30ThreadX_Library.lib. The resulting file sample_threadx.axf is a binary file that
31can be downloaded and executed on Cortex-M4 hardware.
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33
343. System Initialization
35
36The entry point in ThreadX for the Cortex-M4 using Keil tools is at label
37__main. This is defined within the Keil compiler's startup code. In
38addition, this is where all static and global pre-set C variable
39initialization processing takes place.
40
41The ThreadX tx_initialize_low_level.s file is responsible for setting up
42various system data structures, the vector area, and a periodic timer interrupt
43source.
44
45In addition, _tx_initialize_low_level determines the first available
46address for use by the application, which is supplied as the sole input
47parameter to your application definition function, tx_application_define.
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49
504. Register Usage and Stack Frames
51
52The following defines the saved context stack frames for context switches
53that occur as a result of interrupt handling or from thread-level API calls.
54All suspended threads have the same stack frame in the Cortex-M4 version of
55ThreadX. The top of the suspended thread's stack is pointed to by
56tx_thread_stack_ptr in the associated thread control block TX_THREAD.
57
58Non-FPU Stack Frame:
59
60 Stack Offset Stack Contents
61
62 0x00 LR Interrupted LR (LR at time of PENDSV)
63 0x04 r4 Software stacked GP registers
64 0x08 r5
65 0x0C r6
66 0x10 r7
67 0x14 r8
68 0x18 r9
69 0x1C r10
70 0x20 r11
71 0x24 r0 Hardware stacked registers
72 0x28 r1
73 0x2C r2
74 0x30 r3
75 0x34 r12
76 0x38 lr
77 0x3C pc
78 0x40 xPSR
79
80FPU Stack Frame (only interrupted thread with FPU enabled):
81
82 Stack Offset Stack Contents
83
84 0x00 LR Interrupted LR (LR at time of PENDSV)
85 0x04 s16 Software stacked FPU registers
86 0x08 s17
87 0x0C s18
88 0x10 s19
89 0x14 s20
90 0x18 s21
91 0x1C s22
92 0x20 s23
93 0x24 s24
94 0x28 s25
95 0x2C s26
96 0x30 s27
97 0x34 s28
98 0x38 s29
99 0x3C s30
100 0x40 s31
101 0x44 r4 Software stacked registers
102 0x48 r5
103 0x4C r6
104 0x50 r7
105 0x54 r8
106 0x58 r9
107 0x5C r10
108 0x60 r11
109 0x64 r0 Hardware stacked registers
110 0x68 r1
111 0x6C r2
112 0x70 r3
113 0x74 r12
114 0x78 lr
115 0x7C pc
116 0x80 xPSR
117 0x84 s0 Hardware stacked FPU registers
118 0x88 s1
119 0x8C s2
120 0x90 s3
121 0x94 s4
122 0x98 s5
123 0x9C s6
124 0xA0 s7
125 0xA4 s8
126 0xA8 s9
127 0xAC s10
128 0xB0 s11
129 0xB4 s12
130 0xB8 s13
131 0xBC s14
132 0xC0 s15
133 0xC4 fpscr
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135
1365. Improving Performance
137
138The distribution version of ThreadX is built without any compiler
139optimizations. This makes it easy to debug because you can trace or set
140breakpoints inside of ThreadX itself. Of course, this costs some
141performance. To make it run faster, you can change the ThreadX_Library.Uv2
142project to debugging and enable all compiler optimizations.
143
144In addition, you can eliminate the ThreadX basic API error checking by
145compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
146defined.
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148
1496. Interrupt Handling
150
151ThreadX provides complete and high-performance interrupt handling for Cortex-M4
152targets. There are a certain set of requirements that are defined in the
153following sub-sections:
154
155
1566.1 Vector Area
157
158The Cortex-M4 vectors start at the label __tx_vectors. The application may modify
159the vector area according to its needs.
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161
1626.2 Managed Interrupts
163
164ISRs for Cortex-M can be written completely in C (or assembly language) without any
165calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
166access to the ThreadX API that is available to ISRs.
167
168ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
169
170void your_C_isr(void)
171{
172
173 /* ISR processing goes here, including any needed function calls. */
174}
175
176ISRs written in assembly language will take the form:
177
178 EXPORT your_assembly_isr
179your_assembly_isr
180
181 PUSH {r0, lr}
182
183 ; ISR processing goes here, including any needed function calls.
184
185 POP {r0, lr}
186 BX lr
187
188
1897. FPU Support
190
191ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads
192can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread
193context - no additional setup by the application.
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195
196
1978. Revision History
198
199For generic code revision information, please refer to the readme_threadx_generic.txt
200file, which is included in your distribution. The following details the revision
201information associated with this specific port of ThreadX:
202
20304-02-2021 Release 6.1.6 changes:
204 tx_port.h Updated macro definition
205 tx_thread_schedule.s Fix compilation error
206
20703-02-2021 The following files were changed/added for version 6.1.5:
208 tx_thread_schedule.s Added low power feature
209
21009-30-2020 Initial ThreadX 6.1 version for Cortex-M4 using Keil tools.
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212
213Copyright(c) 1996-2020 Microsoft Corporation
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215
216https://azure.com/rtos
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218
