readme_threadx.txt
1 Microsoft's Azure RTOS ThreadX for Cortex-A35
2
3 Using the ARM GNU Compiler & DS
4
51. Import the ThreadX Projects
6
7In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import
8the 'tx' and 'sample_threadx' projects (located in the "example_build" directory)
9into your DS workspace.
10
11
122. Building the ThreadX SMP run-time Library
13
14Building the ThreadX SMP library is easy; simply select the Eclipse project file
15"tx" and then select the build button. You should now observe the compilation
16and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP
17library file tx.a.
18
19
203. Demonstration System
21
22The ThreadX SMP demonstration is designed to execute under the DS-5 debugger on the
23'Debug Cortex-A35x4 SMP' FVP which must be downloaded from the ARM website and
24requires a license.
25
26Building the demonstration is easy; simply select the sample_threadx project, and
27select the build button. Next, in the sample_threadx project, right-click on the
28sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is
29setup for the Cortex-35x4 SMP FVP, so selecting "Debug" will launch the FVP, load
30the sample_threadx.axf ELF file and run to main. You are now ready to execute the
31ThreadX SMP demonstration.
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33
344. System Initialization
35
36The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label
37"start64". This is defined within the GCC compiler's startup code. In addition,
38this is where all static and global pre-set C variable initialization processing
39takes place.
40
41The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the
42first available RAM address for use by the application, which is supplied as the
43sole input parameter to your application definition function, tx_application_define.
44
45
465. Register Usage and Stack Frames
47
48The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers
49for each function. All other registers used by a C function must be preserved
50by the function. ThreadX SMP takes advantage of this in situations where a context
51switch happens as a result of making a ThreadX SMP service call (which is itself a
52C function). In such cases, the saved context of a thread is only the
53non-scratch registers.
54
55The following defines the saved context stack frames for context switches
56that occur as a result of interrupt handling or from thread-level API calls.
57All suspended threads have one of these two types of stack frames. The top
58of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the
59associated thread control block TX_THREAD.
60
61
62FP not enabled and TX_THREAD.tx_thread_fp_enable == 0:
63
64 Offset Interrupted Stack Frame Non-Interrupt Stack Frame
65
66 0x000 SPSR DAIF
67 0x008 ELR 0
68 0x010 x28 x27
69 0x018 reserved x28
70 0x020 x26 x25
71 0x028 x27 x26
72 0x030 x24 x23
73 0x038 x25 x24
74 0x040 x22 x21
75 0x048 x23 x22
76 0x050 x20 x19
77 0x058 x21 x20
78 0x060 x18 x29
79 0x068 x19 x30
80 0x070 x16
81 0x078 x17
82 0x080 x14
83 0x088 x15
84 0x090 x12
85 0x098 x13
86 0x0A0 x10
87 0x0A8 x11
88 0x0B0 x8
89 0x0B8 x9
90 0x0C0 x6
91 0x0C8 x7
92 0x0D0 x4
93 0x0D8 x5
94 0x0E0 x2
95 0x0E8 x3
96 0x0F0 x0
97 0x0F8 x1
98 0x100 x29
99 0x108 x30
100
101
102FP enabled and TX_THREAD.tx_thread_fp_enable == 1:
103
104 Offset Interrupted Stack Frame Non-Interrupt Stack Frame
105
106 0x000 SPSR DAIF
107 0x008 ELR 0
108 0x010 FPSR FPSR
109 0x018 FPCR FPCR
110 0x020 q30 q14
111 0x030 q31 q15
112 0x040 q28 q12
113 0x050 q29 q13
114 0x060 q26 q10
115 0x070 q27 q11
116 0x080 q24 q8
117 0x090 q25 q9
118 0x0A0 q22 x27
119 0x0A8 x28
120 0x0B0 q23 x25
121 0x0B8 x26
122 0x0C0 q20 x23
123 0x0C8 x24
124 0x0D0 q21 x21
125 0x0D8 x22
126 0x0E0 q18 x19
127 0x0E8 x20
128 0x0F0 q19 x29
129 0x0F8 x30
130 0x100 q16
131 0x110 q17
132 0x120 q14
133 0x130 q15
134 0x140 q12
135 0x150 q13
136 0x160 q10
137 0x170 q11
138 0x180 q8
139 0x190 q9
140 0x1A0 q6
141 0x1B0 q7
142 0x1C0 q4
143 0x1D0 q5
144 0x1E0 q2
145 0x1F0 q3
146 0x200 q0
147 0x210 q1
148 0x220 x28
149 0x228 reserved
150 0x230 x26
151 0x238 x27
152 0x240 x24
153 0x248 x25
154 0x250 x22
155 0x258 x23
156 0x260 x20
157 0x268 x21
158 0x270 x18
159 0x278 x19
160 0x280 x16
161 0x288 x17
162 0x290 x14
163 0x298 x15
164 0x2A0 x12
165 0x2A8 x13
166 0x2B0 x10
167 0x2B8 x11
168 0x2C0 x8
169 0x2C8 x9
170 0x2D0 x6
171 0x2D8 x7
172 0x2E0 x4
173 0x2E8 x5
174 0x2F0 x2
175 0x2F8 x3
176 0x300 x0
177 0x308 x1
178 0x310 x29
179 0x318 x30
180
181
182
1836. Improving Performance
184
185The distribution version of ThreadX SMP is built without any compiler optimizations.
186This makes it easy to debug because you can trace or set breakpoints inside of
187ThreadX SMP itself. Of course, this costs some performance. To make it run faster,
188you can change the project settings to the desired compiler optimization level.
189
190In addition, you can eliminate the ThreadX SMP basic API error checking by
191compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
192defined.
193
194
1957. Interrupt Handling
196
197ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A35
198targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following
199format:
200
201 .global irq_handler
202irq_handler:
203 MSR SPSel, 0
204 STP x29, x30, [sp, #-16]!
205 BL _tx_thread_context_save
206
207 /* Your ISR call goes here! */
208 BL application_isr_handler
209
210 B _tx_thread_context_restore
211
212By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1
213and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined.
214
215
2168. ThreadX SMP Timer Interrupt
217
218ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps,
219timeouts, and application timers. Without such a timer interrupt source, these services
220are not functional. However, all other ThreadX services are operational without a
221periodic timer source.
222
223
2249. ARM FP Support
225
226By default, FP support is disabled for each thread. If saving the context of the FP registers
227is needed, the following API call must be made from the context of the application thread - before
228the FP usage:
229
230void tx_thread_fp_enable(void);
231
232After this API is called in the application, FP registers will be saved/restored for this thread if it
233is preempted via an interrupt. All other suspension of the this thread will not require the FP registers
234to be saved/restored.
235
236To disable FP register context saving, simply call the following API:
237
238void tx_thread_fp_disable(void);
239
240
24110. Revision History
242
243For generic code revision information, please refer to the readme_threadx_generic.txt
244file, which is included in your distribution. The following details the revision
245information associated with this specific port of ThreadX SMP:
246
24704-02-2021 Release 6.1.6 changes:
248 tx_port.h Updated macro definition
249
25009-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using ARM GCC and DS tools.
251
252
253Copyright(c) 1996-2020 Microsoft Corporation
254
255
256https://azure.com/rtos
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258
