readme_threadx.txt
1 Microsoft's Azure RTOS ThreadX for Renesas RXv3
2
3 Using the IAR Tools
4
5
61. Building the ThreadX run-time Library
7
8Please see the Samples repository on GitHub for the Azure RTOS demonstrations
9for the RXv3.
10
11
122. Demonstration System
13
14Please see the Samples repository on GitHub for the Azure RTOS demonstrations
15for the RXv3.
16
17
183. System Initialization
19
20The system entry point using the IAR tools is at the label __iar_program_start.
21
22The vector area is setup in the file tx_initialize_low_level.s. This file is also
23responsible for setting up various system data structures, interrupt vectors, and
24the periodic timer interrupt. This file is also an ideal place add hardware
25initialization code.
26
27The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt
28source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the
29interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in
30r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the
31timer parameters as needed.
32
33In addition, _tx_initialize_low_level determines the first available address for use
34by the application, which is supplied as the sole input parameter to your application
35definition function, tx_application_define. The first available memory is determined
36by the location of the FREEMEM section so it should be placed AFTER all other RAM
37sections in your linker control file.
38
39
404. Context Switch, Register Usage and Stack Frames
41
42The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27,
43to perform context switch with the interrupt priority level 1. This ISR is thus reserved
44when using ThreadX and the SWINT should not be manipulated in any way by the application.
45The port will setup the interrupt within _tx_initialize_low_level and the compiler will
46automatically install the necessary interrupt vector. As such no additional initialization
47is necessary by the application.
48
49The following defines the saved context stack frame used by the ThreadX port. The
50state of the CPU registers at the time of a context switch is saved on the running
51thread's stack The top of the suspended thread's stack is pointed to by
52tx_thread_stack_ptr in the associated thread control block TX_THREAD.
53
54 Offset Stack Frame
55
56 0x00 ACC0
57 0x04 ACC1
58 0x08 R6
59 0x0C R7
60 0x10 R8
61 0x14 R9
62 0x18 R10
63 0x1C R11
64 0x20 R12
65 0x24 R13
66 0x28 FPSW
67 0x2C R14
68 0x30 R15
69 0x34 R3
70 0x38 R4
71 0x3C R5
72 0x40 R1
73 0x44 R2
74 0x48 PC - return address
75 0x4C PSW
76
77 Offset Stack Frame with DFPU Register
78
79 0x00 DPSW
80 0x04 DCMR
81 0x08 DECNT
82 0x0C DEPC
83 0x10 DR0
84 0x14 DR1
85 0x18 DR2
86 0x1C DR3
87 0x20 DR4
88 0x24 DR5
89 0x28 DR6
90 0x2C DR7
91 0x30 DR8
92 0x34 DR9
93 0x38 DR10
94 0x3C DR11
95 0x40 DR12
96 0x44 DR13
97 0x48 DR14
98 0x4C DR15
99 0x50 ACC0
100 0x54 ACC1
101 0x58 R6
102 0x5C R7
103 0x60 R8
104 0x64 R9
105 0x68 R10
106 0x6C R11
107 0x70 R12
108 0x74 R13
109 0x78 FPSW
110 0x7C R14
111 0x80 R15
112 0x84 R3
113 0x88 R4
114 0x8C R5
115 0x90 R1
116 0x94 R2
117 0x98 PC - return address
118 0x9C PSW
119
120
121Note: By default IAR does not save the state of the accumulator registers ACC0 and ACC1
122when entering an ISR. This means that if the ISR uses any of the DSP instructions the
123content of those registers could be corrupted. Saving and restoring of the acummulators
124can be enabled by adding the --save_acc command line option.
125
126
1275. Double Precision FPU Instructions Support
128
129The RXv3 architecture supports an optional set of double precision instructions which
130makes use of a new set of registers that must be saved and restored during context
131switches. This feature can be accessed by setting the size of double to 64 bit in the
132compiler options. To reduce the overhead of saving and restoring the FPU registers
133for all threads the RXv3 port allows each thread to enable and disable saving and
134restoring the DFPU registers. By default the feature is disabled for new threads.
135To enable the feature tx_thread_fpu_enable() must be called within the context of every
136thread that will perform FPU operation. The saving and restoring of DFPU registers can
137be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread
138only makes occasional use of the FPU.
139
140
1416. Improving Performance
142
143The distribution version of ThreadX is built without any compiler optimizations. This
144makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself.
145Of course, this costs some performance. To make ThreadX run faster, you can change the
146ThreadX Library project to disable debug information and enable the desired optimizations.
147
148In addition, you can eliminate the ThreadX basic API error checking by compiling your
149application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h
150is included.
151
152
1537. Timer Processing
154
155Timer processign is performed by calling __tx_timer_interrupt(). This should usually be done
156from within the callback of a periodic timer with a period of 100Hz. In the sample projects
157a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source.
158
159
1608. Interrupt Handling
161
162Interrupt handling is unaffected by the ThreadX port as such user interrupts can be
163written according to the toolchain's documentation. It is recommended not to use interrupt
164priority 1 as this is the priority of the context switch interrupt. However using interrupt
165priority 1 won't cause any negative side effectd but doing so may slightly reduce
166performance. Please refer to the toolchain documentation for additional details on how to
167define interrupt service routines.
168
169
1709. Execution Profiling
171
172The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists
173of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation
174of the EPK for generic usage details.
175
176To add the EPK to your RXv3 release make the following modifications:
177
178* Enable the following define for both the Threadx library and the application
179TX_EXECUTION_PROFILE_ENABLE
180
181* Setup CMT1 as a free running 16 bit timer.
182
183* In tx_execution_profile.h, change following around line 52:
184
185#ifdef TX_EXECUTION_64BIT_TIME
186typedef unsigned long long EXECUTION_TIME;
187#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFFFFFFFFFFFFFF
188#else
189typedef unsigned long EXECUTION_TIME;
190#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF
191#endif
192
193/* Define basic constants for the execution profile kit. */
194
195#define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A)
196
197Rebuild the Threadx library and the application.
198Refer to the EPK documentation how to interpret the results.
199
200
20110. Revision History
202
203For generic code revision information, please refer to the readme_threadx_generic.txt
204file, which is included in your distribution. The following details the revision
205information associated with this specific port of ThreadX:
206
20704-25-2022 Release 6.1.11 changes:
208 tx_thread_schedule.s Added low power support
209
21001-31-2022 Release 6.1.10 changes:
211 tx_port.h Removed system state macro, and added
212 missing interrupt control defines
213 tx_timer_interrupt.s Added missing thread preemption logic
214
21510-15-2021 Release 6.1.9 changes:
216 tx_port.h Added FPU support
217 tx_thread_context_restore.s Added FPU support
218 tx_thread_schedule.s Added FPU support
219
22006-02-2021 Initial ThreadX release for the RXv3using IAR tools, version 6.1.7
221
222
223Copyright(c) 1996-2022 Microsoft Corporation
224
225
226https://azure.com/rtos
