readme_threadx.txt
1 Microsoft's Azure RTOS ThreadX for Cortex-M55
2
3 Using the GNU Tools
4
51. Building the ThreadX run-time Library
6
7Import all ThreadX common and port-specific source files into a GNU project.
8Configure the project to build a library rather than an executable. This
9results in the ThreadX run-time library file tx.a, which is needed by
10the application.
11Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
12replace the common files of the same name.
13
142. Demonstration System
15
16No demonstration project is provided.
17
18
193. System Initialization
20
21The entry point in ThreadX for the Cortex-M55 using gnu tools uses the standard GNU
22Cortex-M55 reset sequence. From the reset vector the C runtime will be initialized.
23
24The ThreadX tx_initialize_low_level.S file is responsible for setting up
25various system data structures, the vector area, and a periodic timer interrupt
26source.
27
28In addition, _tx_initialize_low_level determines the first available
29address for use by the application, which is supplied as the sole input
30parameter to your application definition function, tx_application_define.
31
32
334. Register Usage and Stack Frames
34
35The following defines the saved context stack frames for context switches
36that occur as a result of interrupt handling or from thread-level API calls.
37All suspended threads have the same stack frame in the Cortex-M55 version of
38ThreadX. The top of the suspended thread's stack is pointed to by
39tx_thread_stack_ptr in the associated thread control block TX_THREAD.
40
41Non-FPU Stack Frame:
42
43 Stack Offset Stack Contents
44
45 0x00 LR Interrupted LR (LR at time of PENDSV)
46 0x04 r4 Software stacked GP registers
47 0x08 r5
48 0x0C r6
49 0x10 r7
50 0x14 r8
51 0x18 r9
52 0x1C r10
53 0x20 r11
54 0x24 r0 Hardware stacked registers
55 0x28 r1
56 0x2C r2
57 0x30 r3
58 0x34 r12
59 0x38 lr
60 0x3C pc
61 0x40 xPSR
62
63FPU Stack Frame (only interrupted thread with FPU enabled):
64
65 Stack Offset Stack Contents
66
67 0x00 LR Interrupted LR (LR at time of PENDSV)
68 0x04 s16 Software stacked FPU registers
69 0x08 s17
70 0x0C s18
71 0x10 s19
72 0x14 s20
73 0x18 s21
74 0x1C s22
75 0x20 s23
76 0x24 s24
77 0x28 s25
78 0x2C s26
79 0x30 s27
80 0x34 s28
81 0x38 s29
82 0x3C s30
83 0x40 s31
84 0x44 r4 Software stacked registers
85 0x48 r5
86 0x4C r6
87 0x50 r7
88 0x54 r8
89 0x58 r9
90 0x5C r10
91 0x60 r11
92 0x64 r0 Hardware stacked registers
93 0x68 r1
94 0x6C r2
95 0x70 r3
96 0x74 r12
97 0x78 lr
98 0x7C pc
99 0x80 xPSR
100 0x84 s0 Hardware stacked FPU registers
101 0x88 s1
102 0x8C s2
103 0x90 s3
104 0x94 s4
105 0x98 s5
106 0x9C s6
107 0xA0 s7
108 0xA4 s8
109 0xA8 s9
110 0xAC s10
111 0xB0 s11
112 0xB4 s12
113 0xB8 s13
114 0xBC s14
115 0xC0 s15
116 0xC4 fpscr
117
118
1195. Improving Performance
120
121To make ThreadX and the application(s) run faster, you can enable
122all compiler optimizations.
123
124In addition, you can eliminate the ThreadX basic API error checking by
125compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
126defined.
127
128
1296. Interrupt Handling
130
131ThreadX provides complete and high-performance interrupt handling for Cortex-M55
132targets. There are a certain set of requirements that are defined in the
133following sub-sections:
134
135
1366.1 Vector Area
137
138The Cortex-M55 vectors start at the label __tx_vectors or similar. The application may modify
139the vector area according to its needs. There is code in tx_initialize_low_level() that will
140configure the vector base register.
141
142
1436.2 Managed Interrupts
144
145ISRs can be written completely in C (or assembly language) without any calls to
146_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the
147ThreadX API that is available to ISRs.
148
149ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
150
151void your_C_isr(void)
152{
153
154 /* ISR processing goes here, including any needed function calls. */
155}
156
157ISRs written in assembly language will take the form:
158
159
160 .global your_assembly_isr
161 .thumb_func
162your_assembly_isr:
163 PUSH {r0, lr}
164;
165; /* Do interrupt handler work here */
166; /* BL <your interrupt routine in C> */
167
168 POP {r0, lr}
169 BX lr
170
171Note: the Cortex-M55 requires exception handlers to be thumb labels, this implies bit 0 set.
172To accomplish this, the declaration of the label has to be preceded by the assembler directive
173.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to
174be inserted in the correct location in the interrupt vector table. This table is typically
175located in either your runtime startup file or in the tx_initialize_low_level.S file.
176
177
1787. FPU Support
179
180ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads
181can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread
182context.
183
184
1858. Revision History
186
187For generic code revision information, please refer to the readme_threadx_generic.txt
188file, which is included in your distribution. The following details the revision
189information associated with this specific port of ThreadX:
190
19106-02-2021 Release 6.1.7 changes:
192 tx_thread_secure_stack_initialize.S New file
193 tx_thread_schedule.S Added secure stack initialize to SVC hander
194 tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode
195
19604-02-2021 Release 6.1.6 changes:
197 tx_port.h Updated macro definition
198 tx_thread_schedule.s Added low power support
199
20003-02-2021 The following files were changed/added for version 6.1.5:
201 tx_port.h Added ULONG64_DEFINED
202
20309-30-2020 Initial ThreadX 6.1 version for Cortex-M55 using GNU tools.
204
205
206Copyright(c) 1996-2020 Microsoft Corporation
207
208
209https://azure.com/rtos
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211
