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/ThreadX-v6.4.1/ports/xtensa/xcc/src/
Dtx_thread_context_restore.S100 l32i a3, a2, 0 /* decrement interrupt nesting count */
101 addi a3, a3, -1
102 s32i a3, a2, 0
103 bnez a3, .L_tx_thread_nested_restore
117 movi a3, _tx_thread_execute_ptr
120 l32i a3, a3, 0 /* a3 = _tx_thread_execute_ptr (new) */
121 beq a3, a2, .L_tx_thread_no_preempt_restore
123 movi a3, _tx_thread_preempt_disable
124 l32i a3, a3, 0 /* a3 = _tx_thread_preempt_disable */
127 bgei a3, 1, .L_tx_thread_no_preempt_restore
[all …]
Dxtensa_context.S101 s32i a3, sp, XT_STK_A3
121 rsr a3, SAR
122 s32i a3, sp, XT_STK_SAR
125 rsr a3, LBEG
126 s32i a3, sp, XT_STK_LBEG
127 rsr a3, LEND
128 s32i a3, sp, XT_STK_LEND
129 rsr a3, LCOUNT
130 s32i a3, sp, XT_STK_LCOUNT
135 movi a3, 0
[all …]
Dtx_thread_schedule.S81 movi a3, PS_STACK_MASK | PS_DI_MASK /* disable interrupts. */
82 xps a2, a3
121 movi a3, _tx_thread_execute_ptr
124 l32i a2, a3, 0 /* a2 = _tx_thread_execute_ptr */
140 movi a3, _tx_thread_current_ptr
142 s32i a2, a3, 0 /* a2 = _tx_thread_current_ptr (TCB) */
146 addi a3, a0, 1
148 s32i a3, a2, tx_thread_run_count
152 l32i a3, a2, tx_thread_time_slice
153 s32i a3, a0, 0
[all …]
Dtx_timer_interrupt.S125 l32i a3, a2, 0 /* a3 = _tx_timer_system_clock++ */
126 addi a3, a3, 1
127 s32i a3, a2, 0
133 movi a3, xt_tick_divisor
134 l32i a2, a3, 0 /* a2 = comparator increment */
136 rsr a3, XT_CCOMPARE /* a3 = old comparator value */
137 add a4, a3, a2 /* a4 = new comparator value */
217 s32i a3, sp, __tx_timer_interrupt_a3
261 l32i a3, sp, __tx_timer_interrupt_a3
271 sub a4, a4, a3 /* diff = ccount - old comparator */
Dxtensa_vectors.S142 rsr a3, INTERRUPT
144 and a2, a2, a3
197 movi a3, \mask /* a3 = all interrupts at this level */
200 and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */
201 movi a3, _xt_intdata
202 l32i a6, a3, 4 /* a6 = _xt_vpri_mask */
206 s32i a5, a3, 4 /* update _xt_vpri_mask */
207 rsr a3, INTENABLE
208 and a3, a3, a2 /* mask off all bits <= a4 bit */
209 wsr a3, INTENABLE
[all …]
Dxtensa_coproc_handler.S117 movi a3, _xt_coproc_owner_sa
123 addx4 a3, a5, a3 // a3 = &_xt_coproc_owner_sa[n]
124 l32i a2, a3, 0 // a2 = old owner's save area
125 s32i a15, a3, 0 // _xt_coproc_owner_sa[n] = new
155 extui a3, a0, 16, 5 // a3 = CP index = n
170 l16ui a3, a15, XT_CPSTORED // a3 = new owner's CPSTORED
172 bnone a3, a0, .L_check_cs // full CP not saved, check callee-saved
173 xor a3, a3, a0 // CPSTORED bit is set, clear it
174 s16i a3, a15, XT_CPSTORED // update new owner's CPSTORED
177 extui a3, a0, 16, 5 // a3 = CP index = n
[all …]
Dtx_thread_system_return.S136 movi a3, _tx_thread_current_ptr /* a3 = &_tx_thread_current_ptr */
138 l32i a4, a3, 0 /* a4 = _tx_thread_current_ptr */
160 s32i a5, a3, 0 /* Clear _tx_thread_current_ptr */
239 l32i a3, a2, 0 /* a3 points to TCB */
243 s32i a0, a3, tx_thread_solicited
249 s32i sp, a3, tx_thread_stack_ptr
262 s32i a0, a3, tx_thread_time_slice
276 s16i a0, a3, tx_thread_cp_state + XT_CPENABLE
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dinit_caches2.S70 ext a3, v0, CFG1_ILSHIFT, 3 // Extract IS
72 beq a2, a3, Isets_done // if IS = 2
73 li a3, 1024 // sets = 256
74 li a3, 2048 // else sets = 512 Skipped if branch taken
82 add a3, -1 // Decrement set counter
83 bne a3, zero, next_icache_tag // Done yet?
106 ext a3, v0, CFG1_DSSHIFT, 3 // Extract DS
108 beq a2, a3, Dsets_done // if DS = 2
109 li a3, 1024 // sets = 256
110 li a3, 2048 // else sets = 512 Skipped if branch taken
[all …]
Drelease_mp.S59 li a3, 1
66 move a0, a3
71 bne r19_more_cores, a3, powerup_next_core
72 add a3, a3, 1
79 move a0, a3
83 bne r19_more_cores, a3, release_next_core
84 add a3, a3, 1
Dinit_L23caches.S76 li a3, 0x50 // Enable CCA and set to uncached
77 ins a0, a3, 0, 8 // Insert bits
152 move a3, a0
158 add a3, -1 // Decrement set counter
160 bne a3, zero, next_L2cache_tag // Done yet?
192 move a3, a0
198 add a3, -1 // Decrement set counter
199 bne a3, zero, next_L3cache_tag
Djoin_domain.S70 move a3, zero
73 sll a0, a3, 16
81 bne a3, r19_more_cores, next_coherent_core
82 addiu a3, 1
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_caches2.mip70 ext a3, v0, CFG1_ILSHIFT, 3 // Extract IS
72 beq a2, a3, Isets_done // if IS = 2
73 li a3, 1024 // sets = 256
74 li a3, 2048 // else sets = 512 Skipped if branch taken
82 add a3, -1 // Decrement set counter
83 bne a3, zero, next_icache_tag // Done yet?
106 ext a3, v0, CFG1_DSSHIFT, 3 // Extract DS
108 beq a2, a3, Dsets_done // if DS = 2
109 li a3, 1024 // sets = 256
110 li a3, 2048 // else sets = 512 Skipped if branch taken
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a7/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/arm9/gnu/example_build/
Dcrt0.S31 ldr a3, .LC2
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_r4/gnu/example_build/
Dcrt0.S31 ldr a3, .LC2
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/arm11/gnu/example_build/
Dcrt0.S31 ldr a3, .LC2
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_r5/gnu/example_build/
Dcrt0.S31 ldr a3, .LC2
32 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a15/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a8/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a7/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a9/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a5/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a17/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */
/ThreadX-v6.4.1/ports/cortex_a12/gnu/example_build/
Dcrt0.S46 ldr a3, .LC2
47 sub a3, a3, a1 /* Third arg: length of block */

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