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/ThreadX-v6.4.1/ports/arm9/ac5/example_build/
Dtx_initialize_low_level.s65 Timer1Clear EQU 0x0a80000C ; Timer1 Clear Register define
317 LDR r1,=Timer1Clear ; Build address of Timer1 clear register
/ThreadX-v6.4.1/ports/arm11/ac5/example_build/
Dtx_initialize_low_level.s65 Timer1Clear EQU 0x0a80000C ; Timer1 Clear Register define
317 LDR r1,=Timer1Clear ; Build address of Timer1 clear register