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/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c38 #define GIC_REG(offset) *((volatile uint32_t *)(GIC_BASEADDR+offset)) macro
40 #define GICD_CTLR GIC_REG(0x000)
41 #define GICD_ISENABLER(i) GIC_REG(0x100 + 4*(i))
42 #define GICD_ICENABLER(i) GIC_REG(0x180 + 4*(i))
43 #define GICD_ICPENDR(i) GIC_REG(0x280 + 4*(i))
44 #define GICD_ISACTIVER(i) GIC_REG(0x300 + 4*(i))
45 #define GICD_ICACTIVER(i) GIC_REG(0x380 + 4*(i))
46 #define GICD_IPRIORITY(i) GIC_REG(0x400 + 4*(i))
48 #define GICD_ITARGETSR(i) GIC_REG(0x800 + 4*(i))
50 #define GICD_ICFGR(i) GIC_REG(0xc00 + 4*(i))