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/ThreadX-v6.3.0/ports/xtensa/xcc/src/
Dtx_xtensa_stack_error_handler.c112 write(1, "**** Stack overflow in thread \"", 31); in _tx_xtensa_stack_error_handler()
113 write(1, thread->tx_thread_name, strlen(thread->tx_thread_name)); in _tx_xtensa_stack_error_handler()
114 write(1, "\"\n", 2); in _tx_xtensa_stack_error_handler()
/ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_cp0.mip60 mtc0 v1, C0_STATUS // write C0_Status
69 mtc0 v1, C0_WATCHHI // write C0_WatchHi0
72 mtc0 zero, C0_WATCHLO // write C0_WatchLo0
74 mtc0 v1, C0_WATCHHI, 1 // write C0_WatchHi1
77 mtc0 zero, C0_WATCHLO, 1 // write C0_WatchLo1
79 mtc0 v1, C0_WATCHHI, 2 // write C0_WatchHi2
82 mtc0 zero, C0_WATCHLO, 2 // write C0_WatchLo2
84 mtc0 v1, C0_WATCHHI, 3 // write C0_WatchHi3
87 mtc0 zero, C0_WATCHLO, 3 // write C0_WatchLo3
89 mtc0 v1, C0_WATCHHI, 4 // write C0_WatchHi4
[all …]
Dinit_vpe1.mip79 mtc0 v0, C0_MVPCTL // write C0_MVPCtl
97 mtc0 v0, C0_VPECTL // write C0_VPECTL
106 mttc0 v0, C0_TCHALT // write C0_TCHALT
113 mttc0 v0, C0_TCBIND // write C0_TCBind
127 mttc0 v0, C0_VPECONF0 // write C0_VPECONF0
134 mttc0 v0, C0_TCBIND // write C0_TCBIND
146 mttc0 v0, C0_TCSTATUS // write C0_TCSTATUS
190 mttc0 v0, C0_VPECTL // write C0_VPECTL
200 mttc0 v0, C0_VPECONF0 // write C0_VPECONF0
203 mttc0 v0, C0_STATUS // write vpe1 C0_Status
[all …]
Dinit_tlb.mip69 mtc0 zero, C0_ENTRYLO0 // write C0_EntryLo0
70 mtc0 zero, C0_ENTRYLO1 // write C0_EntryLo1
71 mtc0 zero, C0_PAGEMASK // write C0_PageMask
72 mtc0 zero, C0_WIRED // write C0_Wired
76 mtc0 v1, C0_INDEX // write C0_Index
77 mtc0 a0, C0_ENTRYHI // write C0_EntryHi
Djoin_domain.mip68 // Cores other than core 0 can relinquish write access to CM regs here.
/ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dstdio_ghs.c17 long write(int fno, const void *buf, long size) in write() function
/ThreadX-v6.3.0/ports/cortex_m33/ac6/example_build/
DARMCM33_DSP_FP_TZ_config.txt18 … # (bool , init-time) default = '0' : Lock down of SAU registers write
19 … # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
20 … # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
/ThreadX-v6.3.0/ports_module/cortex_m33/ac6/example_build/
DARMCM33_DSP_FP_TZ_config.txt18 … # (bool , init-time) default = '0' : Lock down of SAU registers write
19 … # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
20 … # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
/ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
DMP_Mutexes.s57 STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field
Dv7.s56 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
111 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
170 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
224 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
/ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
DMP_Mutexes.s57 STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field
Dv7.S56 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
111 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
170 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
224 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
Dstartup.S48 Normal_nShared EQU 0x03 ; Outer and Inner write-back, no write-allocate
/ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/example_build/
DMP_Mutexes.S65 STREX r2, r1, [r0] @ Attempt to lock mutex, by write CPU's ID to lock field
Dv7.S95 MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register
153 MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register
215 MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register
271 MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register
/ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/
DMP_Mutexes.s60 STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field
Dv7.s83 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
138 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
197 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
251 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
/ThreadX-v6.3.0/ports/risc-v32/iar/example_build/config/debugger/
Dioriscv.ddf38 ;; AccType Type of access, read-only (R) or read-write (RW)
/ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/
DMP_Mutexes.s60 STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field
Dv7.s83 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
138 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
197 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
251 MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
/ThreadX-v6.3.0/ports/cortex_m0/keil/
Dreadme_threadx.txt34 0x20000000, 0x20080000 [check read and write access]
35 0xE0000000, 0xE8000000 [check read and write access]
/ThreadX-v6.3.0/ports/cortex_m3/keil/
Dreadme_threadx.txt36 0x20000000, 0x20080000 [check read and write access]
37 0xE0000000, 0xE8000000 [check read and write access]
/ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/src/
Dtx_initialize_low_level.a64158 STR w21, [x20, #0x10] // write interrupt ID to GICC_EOIR
/ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/src/
Dtx_thread_smp_protect.S163 DMB @ Ensure write to protection finishes
/ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_smp_protect.S163 DMB @ Ensure write to protection finishes

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