| /ThreadX-v6.3.0/ports/arm11/gnu/example_build/ |
| D | build_threadx.bat | 2 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s tx_initialize_low_level.S
3 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_stack_build.S
4 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_schedule.S
5 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_system_return.S
6 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_context_save.S
7 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_context_restore.S
8 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_interrupt_control.S
9 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_timer_interrupt.S
10 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_interrupt_disable.S
11 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s ../src/tx_thread_interrupt_restore.S
[all …]
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| D | build_threadx_sample.bat | 1 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s reset.S
2 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s crt0.S
3 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s tx_initialize_low_level.S
4 arm-none-eabi-gcc -c -g -mcpu=arm1136j-s -I../../../../common/inc -I../inc sample_threadx.c
5 arm-none-eabi-ld -A arm1136j-s -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample…
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| /ThreadX-v6.3.0/common/inc/ |
| D | tx_queue.h | 92 #define TX_QUEUE_MESSAGE_COPY(s, d, z) \ argument
93 *(d)++ = *(s)++; \
98 *(d)++ = *(s)++; \
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| /ThreadX-v6.3.0/common_smp/inc/ |
| D | tx_queue.h | 92 #define TX_QUEUE_MESSAGE_COPY(s, d, z) \ argument
93 *(d)++ = *(s)++; \
98 *(d)++ = *(s)++; \
|
| /ThreadX-v6.3.0/ports/cortex_m23/iar/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for Cortex-M23
24 __iar_program_start. This is defined within the IAR compiler's startup code.
28 The ThreadX tx_initialize_low_level.s file is responsible for setting up
31 The _tx_initialize_low_level function inside of tx_initialize_low_level.s
35 tx_initialize_low_level.s called FREE_MEM, which must be located after all
44 ThreadX. The top of the suspended thread's stack is pointed to by
70 To make ThreadX and the application(s) run faster, you can enable
81 startup.s file (or similar). The application may modify the vector area according to its needs.
140 tx_thread_secure_stack_initialize.s New file
141 tx_thread_schedule.s Added secure stack initialize to SVC hander
[all …]
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| /ThreadX-v6.3.0/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/ |
| D | readme.txt | 4 Please note that in automatic target-configuration management, changes to the project's device and/…
8 …ways switch back to automatic target-configuration management by checking the "Manage the project's
9 target-configuration automatically" checkbox on the project's Properties > General page.
|
| /ThreadX-v6.3.0/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/ |
| D | readme.txt | 4 Please note that in automatic target-configuration management, changes to the project's device and/…
8 …ways switch back to automatic target-configuration management by checking the "Manage the project's
9 target-configuration automatically" checkbox on the project's Properties > General page.
|
| /ThreadX-v6.3.0/ports/cortex_a8/gnu/example_build/ |
| D | build_threadx_sample.bat | 4 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 MP_GIC.s
5 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 MP_PrivateTimer.s
6 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 V7.s
|
| /ThreadX-v6.3.0/ports/cortex_a9/gnu/example_build/ |
| D | build_threadx_sample.bat | 4 arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_GIC.s
5 arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_PrivateTimer.s
6 arm-none-eabi-gcc -c -g -mcpu=cortex-a9 V7.s
|
| /ThreadX-v6.3.0/ports/cortex_a7/gnu/example_build/ |
| D | build_threadx_sample.bat | 4 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 MP_GIC.s
5 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 MP_PrivateTimer.s
6 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 V7.s
|
| /ThreadX-v6.3.0/ports/cortex_a5/gnu/example_build/ |
| D | build_threadx_sample.bat | 4 arm-none-eabi-gcc -c -g -mcpu=cortex-a5 MP_GIC.s
5 arm-none-eabi-gcc -c -g -mcpu=cortex-a5 MP_PrivateTimer.s
6 arm-none-eabi-gcc -c -g -mcpu=cortex-a5 V7.s
|
| /ThreadX-v6.3.0/ports/arc_em/metaware/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for ARC EM
40 This is defined within the crt1.s file supplied by MetaWare. In addition,
46 is located in the file tx_initialize_low_level.s. This function is
51 which is referenced in tx_initialize_low_level.s and located in the
68 of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the
164 preservation by the application's ISR. ISRs that do not use the ThreadX
180 setup code in tx_initialize_low_level.s.
187 each thread's execution. In addition, the SC bit of STATUS32 is set to enable the stack
202 exception defined in tx_initialize_low_level.s. Processing for this exception is
214 tx_initialize_low_level.s Modified comments
[all …]
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| /ThreadX-v6.3.0/ports/cortex_m85/iar/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for Cortex-M85
24 __iar_program_start. This is defined within the IAR compiler's startup code.
28 The ThreadX tx_initialize_low_level.s file is responsible for setting up
31 The _tx_initialize_low_level function inside of tx_initialize_low_level.s
35 tx_initialize_low_level.s called FREE_MEM, which must be located after all
44 ThreadX. The top of the suspended thread's stack is pointed to by
127 To make ThreadX and the application(s) run faster, you can enable
138 startup.s file (or similar). The application may modify the vector area according to its needs.
203 tx_thread_secure_stack_initialize.s New file
204 tx_thread_schedule.s Added secure stack initialize to SVC hander
[all …]
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| /ThreadX-v6.3.0/ports/cortex_m33/iar/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for Cortex-M33
24 __iar_program_start. This is defined within the IAR compiler's startup code.
28 The ThreadX tx_initialize_low_level.s file is responsible for setting up
31 The _tx_initialize_low_level function inside of tx_initialize_low_level.s
35 tx_initialize_low_level.s called FREE_MEM, which must be located after all
44 ThreadX. The top of the suspended thread's stack is pointed to by
127 To make ThreadX and the application(s) run faster, you can enable
138 startup.s file (or similar). The application may modify the vector area according to its needs.
203 tx_thread_secure_stack_initialize.s New file
204 tx_thread_schedule.s Added secure stack initialize to SVC hander
[all …]
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| /ThreadX-v6.3.0/ports/cortex_m55/iar/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for Cortex-M55
24 __iar_program_start. This is defined within the IAR compiler's startup code.
28 The ThreadX tx_initialize_low_level.s file is responsible for setting up
31 The _tx_initialize_low_level function inside of tx_initialize_low_level.s
35 tx_initialize_low_level.s called FREE_MEM, which must be located after all
44 ThreadX. The top of the suspended thread's stack is pointed to by
127 To make ThreadX and the application(s) run faster, you can enable
138 startup.s file (or similar). The application may modify the vector area according to its needs.
203 tx_thread_secure_stack_initialize.s New file
204 tx_thread_schedule.s Added secure stack initialize to SVC hander
[all …]
|
| /ThreadX-v6.3.0/ports_arch/ARMv8-M/threadx/iar/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for Cortex-Mxx
24 __iar_program_start. This is defined within the IAR compiler's startup code.
28 The ThreadX tx_initialize_low_level.s file is responsible for setting up
31 The _tx_initialize_low_level function inside of tx_initialize_low_level.s
35 tx_initialize_low_level.s called FREE_MEM, which must be located after all
44 ThreadX. The top of the suspended thread's stack is pointed to by
127 To make ThreadX and the application(s) run faster, you can enable
138 startup.s file (or similar). The application may modify the vector area according to its needs.
203 tx_thread_secure_stack_initialize.s New file
204 tx_thread_schedule.s Added secure stack initialize to SVC hander
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_m0/iar/ |
| D | readme_threadx.txt | 1 Microsoft's Azure RTOS ThreadX for Cortex-M0
26 binary file that can be downloaded and executed on IAR's Cortex-M0 simulator.
32 __iar_program_start. This is defined within the IAR compiler's startup code.
36 The ThreadX tx_initialize_low_level.s file is responsible for setting up
38 By default, the vector area is defined at the top of cstartup_M.s, which is
41 The _tx_initialize_low_level function inside of tx_initialize_low_level.s
45 tx_initialize_low_level.s called FREE_MEM, which must be located after all
54 ThreadX. The top of the suspended thread's stack is pointed to by
101 The Cortex-M3 vectors start at the label __vector_table and is defined in cstartup_M.s.
155 tx_thread_schedule.s Added low power feature
[all …]
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| /ThreadX-v6.3.0/ports_smp/arc_hs_smp/metaware/src/ |
| D | tx_thread_smp_initialize_wait.s | 110 ; /* Clear this core's system state variable. */
114 ; /* Now wait for core 0 to finish it's initialization. */
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| /ThreadX-v6.3.0/common/src/ |
| D | tx_misra.c | 184 ULONG *s, *d; in _tx_misra_message_copy() local
187 s = *source; in _tx_misra_message_copy()
191 *(d) = *(s); in _tx_misra_message_copy()
193 (s)++; in _tx_misra_message_copy()
199 *(d) = *(s); in _tx_misra_message_copy()
201 (s)++; in _tx_misra_message_copy()
206 *source = s; in _tx_misra_message_copy()
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| /ThreadX-v6.3.0/common_smp/src/ |
| D | tx_misra.c | 182 ULONG *s, *d; in _tx_misra_message_copy() local
185 s = *source; in _tx_misra_message_copy()
189 *(d) = *(s); in _tx_misra_message_copy()
191 (s)++; in _tx_misra_message_copy()
197 *(d) = *(s); in _tx_misra_message_copy()
199 (s)++; in _tx_misra_message_copy()
204 *source = s; in _tx_misra_message_copy()
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| /ThreadX-v6.3.0/ports/rxv1/ccrx/src/ |
| D | tx_thread_system_return.src | 76 ;/* 10-15-2021 William E. Lamie Modified comment(s), and */
79 ;/* 01-31-2022 William E. Lamie Modified comment(s), */
81 ;/* 04-25-2022 William E. Lamie Modified comment(s), */
|
| /ThreadX-v6.3.0/ports/rxv2/ccrx/src/ |
| D | tx_thread_system_return.src | 76 ;/* 10-15-2021 William E. Lamie Modified comment(s), and */
79 ;/* 01-31-2022 William E. Lamie Modified comment(s), */
81 ;/* 04-25-2022 William E. Lamie Modified comment(s), */
|
| /ThreadX-v6.3.0/ports/rxv3/ccrx/src/ |
| D | tx_thread_system_return.src | 76 ;/* 10-15-2021 William E. Lamie Modified comment(s), and */
79 ;/* 01-31-2022 William E. Lamie Modified comment(s), */
81 ;/* 04-25-2022 William E. Lamie Modified comment(s), */
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/ |
| D | MP_GIC.s | 35 LDR r1, [r0] ; Read the GIC's Enable Register (ICDDCR)
53 LDR r1, [r0] ; Read the GIC's Enable Register (ICDDCR)
|
| /ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/ |
| D | MP_GIC.S | 35 LDR r1, [r0] ; Read the GIC's Enable Register (ICDDCR)
53 LDR r1, [r0] ; Read the GIC's Enable Register (ICDDCR)
|
