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/ThreadX-v6.3.0/ports/cortex_r4/ac5/example_build/
Dbuild_threadx.bat2 armasm -g --cpu=cortex-r4 --apcs=interwork tx_initialize_low_level.s
3 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_stack_build.s
4 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_schedule.s
5 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_system_return.s
6 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_context_save.s
7 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_context_restore.s
8 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_interrupt_control.s
9 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_timer_interrupt.s
10 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_fiq_context_restore.s
11 armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_fiq_context_save.s
[all …]
/ThreadX-v6.3.0/ports/cortex_r4/gnu/example_build/
Dbuild_threadx.bat2 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 tx_initialize_low_level.S
3 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_stack_build.S
4 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_schedule.S
5 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_system_return.S
6 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_context_save.S
7 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_context_restore.S
8 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_interrupt_control.S
9 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_timer_interrupt.S
10 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_interrupt_disable.S
11 arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_interrupt_restore.S
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/src/
Dtx_thread_smp_protect.S95 PUSH {r4-r6} @ Save registers we'll be using
146 LDR r4, =_tx_thread_smp_protect_wait_list_tail
147 LDR r4, [r4]
148 CMP r3, r4
156 STREX r4, r3, [r2, #0] @ Attempt to get the protection
157 CMP r4, #0
176 LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list
177 LDR r4, [r4, r3, LSL #2] @ Get the value at the head index
179 CMP r1, r4
217 LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_smp_protect.S95 PUSH {r4-r6} @ Save registers we'll be using
146 LDR r4, =_tx_thread_smp_protect_wait_list_tail
147 LDR r4, [r4]
148 CMP r3, r4
156 STREX r4, r3, [r2, #0] @ Attempt to get the protection
157 CMP r4, #0
176 LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list
177 LDR r4, [r4, r3, LSL #2] @ Get the value at the head index
179 CMP r1, r4
217 LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/src/
Dtx_thread_smp_protect.S93 PUSH {r4-r6} @ Save registers we'll be using
144 LDR r4, =_tx_thread_smp_protect_wait_list_tail
145 LDR r4, [r4]
146 CMP r3, r4
154 STREX r4, r3, [r2, #0] @ Attempt to get the protection
155 CMP r4, #0
174 LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list
175 LDR r4, [r4, r3, LSL #2] @ Get the value at the head index
177 CMP r1, r4
215 LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_smp_protect.s91 PUSH {r4-r6} ; Save registers we'll be using
142 LDR r4, =_tx_thread_smp_protect_wait_list_tail
143 LDR r4, [r4]
144 CMP r3, r4
152 STREX r4, r3, [r2, #0] ; Attempt to get the protection
153 CMP r4, #0
172 LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list
173 LDR r4, [r4, r3, LSL #2] ; Get the value at the head index
175 CMP r1, r4
213 LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_smp_protect.s93 PUSH {r4-r6} ; Save registers we'll be using
144 LDR r4, =_tx_thread_smp_protect_wait_list_tail
145 LDR r4, [r4]
146 CMP r3, r4
154 STREX r4, r3, [r2, #0] ; Attempt to get the protection
155 CMP r4, #0
174 LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list
175 LDR r4, [r4, r3, LSL #2] ; Get the value at the head index
177 CMP r1, r4
215 LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_smp_protect.s91 PUSH {r4-r6} ; Save registers we'll be using
142 LDR r4, =_tx_thread_smp_protect_wait_list_tail
143 LDR r4, [r4]
144 CMP r3, r4
152 STREX r4, r3, [r2, #0] ; Attempt to get the protection
153 CMP r4, #0
172 LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list
173 LDR r4, [r4, r3, LSL #2] ; Get the value at the head index
175 CMP r1, r4
213 LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core
[all …]
/ThreadX-v6.3.0/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_system_return.s95 PUSH {r4-r11, lr} // Save minimal context
97 LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr
98 LDR r5, [r4] // Pickup current thread pointer
130 MOV r3, r4 // Pickup address of current ptr
141 MOV r4, #0 // Build clear value
147 STR r4, [r2] // Clear time-slice
154 STR r4, [r3] // Clear current thread pointer
/ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_system_return.s81 STMDB sp!, {r4-r11, lr} // Save minimal context
96 VMRS r4, FPSCR // Pickup the FPSCR
97 STR r4, [sp, #-4]! // Save FPSCR
101 MOV r4, #0 // Build a solicited stack type
103 STMDB sp!, {r4-r5} // Save type and CPSR
117 MOV r4, r0 // Save r0
122 MOV r0, r4 // Recover r4
140 MOV r4, #0 // Build clear value
148 STR r4, [r2, #0] // Clear time-slice
157 STR r4, [r3, #0] // Clear current thread pointer
/ThreadX-v6.3.0/ports_module/cortex_m7/gnu/example_build/
Dgcc_setup.s10 STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers
13 ldr r4, =__RAM_segment_start__
22 sub r1,r1, r4
25 sub r2,r2,r4
34 cmp r6, r4 // Is it in the code or data area?
36 sub r6, r6, r4 // Compute offset of data area
56 sub r1,r1, r4
59 sub r2,r2,r4
66 sub r0,r0,r4
69 sub r1,r1,r4
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m33/gnu/example_build/
Dgcc_setup.s10 STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers
13 ldr r4, =__RAM_segment_start__
22 sub r1,r1, r4
25 sub r2,r2,r4
34 cmp r6, r4 // Is it in the code or data area?
36 sub r6, r6, r4 // Compute offset of data area
56 sub r1,r1, r4
59 sub r2,r2,r4
66 sub r0,r0,r4
69 sub r1,r1,r4
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m4/gnu/example_build/
Dgcc_setup.s10 STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers
13 ldr r4, =__RAM_segment_start__
22 sub r1,r1, r4
25 sub r2,r2,r4
34 cmp r6, r4 // Is it in the code or data area?
36 sub r6, r6, r4 // Compute offset of data area
56 sub r1,r1, r4
59 sub r2,r2,r4
66 sub r0,r0,r4
69 sub r1,r1,r4
[all …]
/ThreadX-v6.3.0/ports_module/cortex_a7/gnu/example_build/
Dgcc_setup.S18 STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers
21 ldr r4, =__RAM_segment_start__
30 sub r1,r1, r4
33 sub r2,r2,r4
42 cmp r6, r4 // Is it in the code or data area?
44 sub r6, r6, r4 // Compute offset of data area
64 sub r1,r1, r4
67 sub r2,r2,r4
74 sub r0,r0,r4
77 sub r1,r1,r4
[all …]
/ThreadX-v6.3.0/ports_module/cortex_m3/gnu/example_build/
Dgcc_setup.s10 STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers
13 ldr r4, =__RAM_segment_start__
22 sub r1,r1, r4
25 sub r2,r2,r4
34 cmp r6, r4 // Is it in the code or data area?
36 sub r6, r6, r4 // Compute offset of data area
56 sub r1,r1, r4
59 sub r2,r2,r4
66 sub r0,r0,r4
69 sub r1,r1,r4
[all …]
/ThreadX-v6.3.0/ports/cortex_m3/gnu/src/
Dtx_thread_schedule.S172 STMDB r12!, {r4-r11} // Save its remaining registers
179 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
184 LDR r5, [r4] // Pickup current time-slice
194 STR r3, [r4] // Clear time-slice
215 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
216 MSR BASEPRI, r4
225 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
232 STR r5, [r4] // Setup global time-slice
251 LDMIA r12!, {r4-r11} // Recover thread's registers
292 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports/cortex_m3/iar/src/
Dtx_thread_schedule.s166 STMDB r12!, {r4-r11} // Save its remaining registers
173 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
178 LDR r5, [r4] // Pickup current time-slice
188 STR r3, [r4] // Clear time-slice
209 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
210 MSR BASEPRI, r4
219 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
226 STR r5, [r4] // Setup global time-slice
245 LDMIA r12!, {r4-r11} // Recover thread's registers
286 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports/cortex_m7/gnu/src/
Dtx_thread_schedule.S172 STMDB r12!, {r4-r11} // Save its remaining registers
179 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
184 LDR r5, [r4] // Pickup current time-slice
194 STR r3, [r4] // Clear time-slice
215 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
216 MSR BASEPRI, r4
225 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
232 STR r5, [r4] // Setup global time-slice
251 LDMIA r12!, {r4-r11} // Recover thread's registers
292 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports/cortex_m7/iar/src/
Dtx_thread_schedule.s166 STMDB r12!, {r4-r11} // Save its remaining registers
173 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
178 LDR r5, [r4] // Pickup current time-slice
188 STR r3, [r4] // Clear time-slice
209 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
210 MSR BASEPRI, r4
219 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
226 STR r5, [r4] // Setup global time-slice
245 LDMIA r12!, {r4-r11} // Recover thread's registers
286 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports/cortex_m4/gnu/src/
Dtx_thread_schedule.S172 STMDB r12!, {r4-r11} // Save its remaining registers
179 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
184 LDR r5, [r4] // Pickup current time-slice
194 STR r3, [r4] // Clear time-slice
215 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
216 MSR BASEPRI, r4
225 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
232 STR r5, [r4] // Setup global time-slice
251 LDMIA r12!, {r4-r11} // Recover thread's registers
292 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports/cortex_m4/iar/src/
Dtx_thread_schedule.s166 STMDB r12!, {r4-r11} // Save its remaining registers
173 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
178 LDR r5, [r4] // Pickup current time-slice
188 STR r3, [r4] // Clear time-slice
209 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
210 MSR BASEPRI, r4
219 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
226 STR r5, [r4] // Setup global time-slice
245 LDMIA r12!, {r4-r11} // Recover thread's registers
286 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-M/threadx/gnu/src/
Dtx_thread_schedule.S172 STMDB r12!, {r4-r11} // Save its remaining registers
179 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
184 LDR r5, [r4] // Pickup current time-slice
194 STR r3, [r4] // Clear time-slice
215 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
216 MSR BASEPRI, r4
225 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
232 STR r5, [r4] // Setup global time-slice
251 LDMIA r12!, {r4-r11} // Recover thread's registers
292 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-M/threadx/iar/src/
Dtx_thread_schedule.s166 STMDB r12!, {r4-r11} // Save its remaining registers
173 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
178 LDR r5, [r4] // Pickup current time-slice
188 STR r3, [r4] // Clear time-slice
209 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
210 MSR BASEPRI, r4
219 LDR r4, =_tx_timer_time_slice // Build address of time-slice variable
226 STR r5, [r4] // Setup global time-slice
245 LDMIA r12!, {r4-r11} // Recover thread's registers
286 MOV r4, #0 // Disable BASEPRI masking (enable interrupts)
[all …]
/ThreadX-v6.3.0/ports_module/cortex_r4/ac6/module_manager/src/
Dtx_thread_system_return.S96 STMDB sp!, {r4-r11, lr} // Save minimal context
104 VMRS r4, FPSCR // Pickup the FPSCR
105 STR r4, [sp, #-4]! // Save FPSCR
141 MOV r4, #0 // Build clear value
149 STR r4, [r2, #0] // Clear time-slice
158 STR r4, [r5, #0] // Clear current thread pointer
/ThreadX-v6.3.0/ports/cortex_r4/ac6/src/
Dtx_thread_system_return.S96 STMDB sp!, {r4-r11, lr} // Save minimal context
104 VMRS r4, FPSCR // Pickup the FPSCR
105 STR r4, [sp, #-4]! // Save FPSCR
141 MOV r4, #0 // Build clear value
149 STR r4, [r2, #0] // Clear time-slice
158 STR r4, [r5, #0] // Clear current thread pointer

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