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/ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_smp_initialize_wait.s82 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
83 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
84 LSL r10, r10, #2 // Build offset to array indexes
90 ADD r3, r3, r10 // Build index into the system state array
111 ADD r3, r3, r10 // Build index into the system state array
Dtx_thread_context_save.s90 STMDB sp!, {r0, r10, r12, lr} // Store other registers
98 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
99 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
100 LSL r12, r10, #2 // Build offset to array indexes
115 MOV r10, #0 // Clear stack limit
150 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
Dtx_thread_context_restore.s109 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
110 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
111 LSL r12, r10, #2 // Build offset to array indexes
130 LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
151 … CMP r2, r10 // Is the owning core the same as the protected core?
175 LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
185 LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers
199 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
200 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
201 LSL r12, r10, #2 // Build offset to array indexes
Dtx_thread_vectored_context_save.s88 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
89 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
90 LSL r12, r10, #2 // Build offset to array indexes
107 MOV r10, #0 // Clear stack limit
148 MOV r10, #0 // Clear stack limit
176 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a9/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a8/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a12/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a15/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a7/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a5/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a17/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/example_build/
Dv7.S89 MOV r10, #0
92 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
97 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
112 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
121 ADD r10, r10, #2 // increment the cache number
122 CMP r3, r10
147 MOV r10, #0
150 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
155 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
170 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/example_build/
Dv7.S89 MOV r10, #0
92 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
97 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
112 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
121 ADD r10, r10, #2 // increment the cache number
122 CMP r3, r10
147 MOV r10, #0
150 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
155 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
170 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.3.0/ports/cortex_a9/gnu/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a8/ac6/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a8/gnu/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a9/ac6/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a12/gnu/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a15/ac6/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a15/gnu/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a7/ac6/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a17/gnu/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit
/ThreadX-v6.3.0/ports/cortex_a12/ac6/src/
Dtx_thread_context_save.S112 STMDB sp!, {r0, r10, r12, lr} // Store other registers
116 MOV r10, #0 // Clear stack limit
144 STMDB sp!, {r2, r10, r12, lr} // Store other registers
146 MOV r10, #0 // Clear stack limit
166 MOV r10, #0 // Clear stack limit

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