| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/example_build/ |
| D | MP_SCU.S | 26 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
28 LDR r0, [r0, #0x004] // Read SCU Configuration register
29 AND r0, r0, #0x3 // Bits 1:0 gives the number of cores-1
30 ADD r0, r0, #1
46 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
48 LDR r1, [r0, #0x0] // Read the SCU Control Register
50 STR r1, [r0, #0x0] // Write back modifed value
66 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
68 LDR r0, [r0, #0x004] // Read SCU Configuration register
69 MOV r0, r0, LSR #4 // Bits 7:4 gives the cores in SMP mode, shift then mask
[all …]
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/example_build/ |
| D | MP_SCU.S | 26 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
28 LDR r0, [r0, #0x004] // Read SCU Configuration register
29 AND r0, r0, #0x3 // Bits 1:0 gives the number of cores-1
30 ADD r0, r0, #1
46 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
48 LDR r1, [r0, #0x0] // Read the SCU Control Register
50 STR r1, [r0, #0x0] // Write back modifed value
66 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
68 LDR r0, [r0, #0x004] // Read SCU Configuration register
69 MOV r0, r0, LSR #4 // Bits 7:4 gives the cores in SMP mode, shift then mask
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m23/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 90 MOVW r0, #0 // Build value for TX_FALSE
92 STR r0, [r2, #0] // Clear preempt disable flag
95 LDR r0, =0xE000ED24 // Build SHCSR address
97 STR r1, [r0] //
103 LDR r0, =0x10000000 // Load PENDSVSET bit
105 STR r0, [r1] // Set PENDSVBIT in ICSR
130 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
131 LDR r1, [r0] // Pickup the current thread pointer
133 LDR r0, =0xE000ED24 // Build SHCSR address
134 LDR r1, [r0] // Pickup SHCSR
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m23/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 86 MOVW r0, #0 // Build value for TX_FALSE
88 STR r0, [r2, #0] // Clear preempt disable flag
91 LDR r0, =0xE000ED24 // Build SHCSR address
93 STR r1, [r0] //
99 LDR r0, =0x10000000 // Load PENDSVSET bit
101 STR r0, [r1] // Set PENDSVBIT in ICSR
126 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
127 LDR r1, [r0] // Pickup the current thread pointer
129 LDR r0, =0xE000ED24 // Build SHCSR address
130 LDR r1, [r0] // Pickup SHCSR
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m23/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 96 MOVW r0, #0 // Build value for TX_FALSE
98 STR r0, [r2, #0] // Clear preempt disable flag
101 LDR r0, =0xE000ED24 // Build SHCSR address
103 STR r1, [r0] //
109 LDR r0, =0x10000000 // Load PENDSVSET bit
111 STR r0, [r1] // Set PENDSVBIT in ICSR
134 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
135 LDR r1, [r0] // Pickup the current thread pointer
137 LDR r0, =0xE000ED24 // Build SHCSR address
138 LDR r1, [r0] // Pickup SHCSR
[all …]
|
| /ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a8/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a9/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a12/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a15/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a7/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a5/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a17/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/ |
| D | startup.S | 69 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
70 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
71 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
72 BIC r0, r0, #0x1 // Clear M bit 0 to disable MPU
74 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
85 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
86 ORR r0, r0, #(0x1 << 17) // Enable RSDIS bit 17 to disable the return stack
87 ORR r0, r0, #(0x1 << 16) // Clear BP bit 15 and set BP bit 16:
88 … BIC r0, r0, #(0x1 << 15) // Branch always not taken and history table updates disabled
89 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_r4/ac6/example_build/sample_threadx/ |
| D | startup.S | 69 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
70 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
71 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
72 BIC r0, r0, #0x1 // Clear M bit 0 to disable MPU
74 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
85 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
86 ORR r0, r0, #(0x1 << 17) // Enable RSDIS bit 17 to disable the return stack
87 ORR r0, r0, #(0x1 << 16) // Clear BP bit 15 and set BP bit 16:
88 … BIC r0, r0, #(0x1 << 15) // Branch always not taken and history table updates disabled
89 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m0+/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 90 MOVS r0, #0 // Build value for TX_FALSE
92 STR r0, [r2, #0] // Clear preempt disable flag
98 LDR r0, =0x10000000 // Load PENDSVSET bit
100 STR r0, [r1] // Set PENDSVBIT in ICSR
130 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
131 LDR r1, [r0] // Pickup the current thread pointer
133 MRS r0, CONTROL // Pickup current CONTROL register
134 STR r0, [r2, #24] // Save CONTROL
137 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
138 STR r0, [r2, #32] // Save r0
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m0+/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 90 MOVS r0, #0 // Build value for TX_FALSE
92 STR r0, [r2, #0] // Clear preempt disable flag
98 LDR r0, =0x10000000 // Load PENDSVSET bit
100 STR r0, [r1] // Set PENDSVBIT in ICSR
130 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
131 LDR r1, [r0] // Pickup the current thread pointer
133 MRS r0, CONTROL // Pickup current CONTROL register
134 STR r0, [r2, #24] // Save CONTROL
137 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
138 STR r0, [r2, #32] // Save r0
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m0+/iar/module_manager/src/ |
| D | tx_thread_schedule.S | 91 MOVS r0, #0 // Build value for TX_FALSE
93 STR r0, [r2, #0] // Clear preempt disable flag
99 LDR r0, =0x10000000 // Load PENDSVSET bit
101 STR r0, [r1] // Set PENDSVBIT in ICSR
122 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
123 LDR r1, [r0] // Pickup the current thread pointer
125 MRS r0, CONTROL // Pickup current CONTROL register
126 STR r0, [r2, #24] // Save CONTROL
129 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
130 STR r0, [r2, #32] // Save r0
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m7/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 99 MOV r0, #0 // Build value for TX_FALSE
101 STR r0, [r2, #0] // Clear preempt disable flag
105 MRS r0, CONTROL // Pickup current CONTROL register
106 BIC r0, r0, #4 // Clear the FPCA bit
107 MSR CONTROL, r0 // Setup new CONTROL register
111 LDR r0, =0xE000ED24 // Build SHCSR address
113 STR r1, [r0] //
120 MOV r0, #0x10000000 // Load PENDSVSET bit
122 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m7/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 101 MOV r0, #0 // Build value for TX_FALSE
103 STR r0, [r2, #0] // Clear preempt disable flag
107 MRS r0, CONTROL // Pickup current CONTROL register
108 BIC r0, r0, #4 // Clear the FPCA bit
109 MSR CONTROL, r0 // Setup new CONTROL register
113 LDR r0, =0xE000ED24 // Build SHCSR address
115 STR r1, [r0] //
122 MOV r0, #0x10000000 // Load PENDSVSET bit
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
156 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m7/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 101 MOV r0, #0 // Build value for TX_FALSE
103 STR r0, [r2, #0] // Clear preempt disable flag
107 MRS r0, CONTROL // Pickup current CONTROL register
108 BIC r0, r0, #4 // Clear the FPCA bit
109 MSR CONTROL, r0 // Setup new CONTROL register
113 LDR r0, =0xE000ED24 // Build SHCSR address
115 STR r1, [r0] //
122 MOV r0, #0x10000000 // Load PENDSVSET bit
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
156 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m7/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 95 MOV r0, #0 // Build value for TX_FALSE
97 STR r0, [r2, #0] // Clear preempt disable flag
101 MRS r0, CONTROL // Pickup current CONTROL register
102 BIC r0, r0, #4 // Clear the FPCA bit
103 MSR CONTROL, r0 // Setup new CONTROL register
107 LDR r0, =0xE000ED24 // Build SHCSR address
109 STR r1, [r0] //
116 MOV r0, #0x10000000 // Load PENDSVSET bit
118 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m4/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 99 MOV r0, #0 // Build value for TX_FALSE
101 STR r0, [r2, #0] // Clear preempt disable flag
105 MRS r0, CONTROL // Pickup current CONTROL register
106 BIC r0, r0, #4 // Clear the FPCA bit
107 MSR CONTROL, r0 // Setup new CONTROL register
111 LDR r0, =0xE000ED24 // Build SHCSR address
113 STR r1, [r0] //
120 MOV r0, #0x10000000 // Load PENDSVSET bit
122 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
147 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m4/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 101 MOV r0, #0 // Build value for TX_FALSE
103 STR r0, [r2, #0] // Clear preempt disable flag
107 MRS r0, CONTROL // Pickup current CONTROL register
108 BIC r0, r0, #4 // Clear the FPCA bit
109 MSR CONTROL, r0 // Setup new CONTROL register
113 LDR r0, =0xE000ED24 // Build SHCSR address
115 STR r1, [r0] //
122 MOV r0, #0x10000000 // Load PENDSVSET bit
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
156 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_m4/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 101 MOV r0, #0 // Build value for TX_FALSE
103 STR r0, [r2, #0] // Clear preempt disable flag
107 MRS r0, CONTROL // Pickup current CONTROL register
108 BIC r0, r0, #4 // Clear the FPCA bit
109 MSR CONTROL, r0 // Setup new CONTROL register
113 LDR r0, =0xE000ED24 // Build SHCSR address
115 STR r1, [r0] //
122 MOV r0, #0x10000000 // Load PENDSVSET bit
124 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
156 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
