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Searched refs:IRQ_DISABLE (Results 1 – 25 of 52) sorted by relevance

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/ThreadX-v6.3.0/ports/cortex_a9/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a8/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a8/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a9/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a12/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a15/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a15/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a7/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a7/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a5/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a5/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a12/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a17/ac6/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a17/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 // IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_irq_nesting_start.s30 IRQ_DISABLE = 0x80 // IRQ disable bit define
98 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_irq_nesting_start.s23 IRQ_DISABLE EQU 0x80 // IRQ disable bit define
83 BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a9/iar/src/
Dtx_thread_irq_nesting_start.s34 IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit label
95 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a8/iar/src/
Dtx_thread_irq_nesting_start.s34 IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit label
95 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/arm9/iar/src/
Dtx_thread_irq_nesting_start.s34 IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit label
95 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/arm11/iar/src/
Dtx_thread_irq_nesting_start.s34 IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit label
95 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a7/iar/src/
Dtx_thread_irq_nesting_start.s34 IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit label
95 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/cortex_a5/iar/src/
Dtx_thread_irq_nesting_start.s34 IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit label
95 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
/ThreadX-v6.3.0/ports/arm11/gnu/src/
Dtx_thread_irq_nesting_start.S26 IRQ_DISABLE = 0x80 @ IRQ disable bit define
96 BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR
/ThreadX-v6.3.0/ports_module/cortex_a7/iar/module_manager/src/
Dtx_thread_irq_nesting_start.s25 IRQ_DISABLE EQU 0x80 ; IRQ disable bit define
94 BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR

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