Home
last modified time | relevance | path

Searched refs:GIC_SH_WEDGE (Results 1 – 9 of 9) sorted by relevance

/ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_smp_core_preempt.S24 #define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. … macro
74 la $8, GIC_SH_WEDGE # Build address
Dtx_initialize_low_level.S24 #define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. */ macro
/ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/src/
Dtx_thread_smp_core_preempt.mip24 #define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. …
74 la $8, GIC_SH_WEDGE # Build address
Dtx_initialize_low_level.mip24 #define GIC_SH_WEDGE 0xbbdc0280 /* For Inter-processor interrupts on MALTA board. */
204 li $8, GIC_SH_WEDGE #
/ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dstart.S125 li k0, (GIC_SH_WEDGE | GIC_BASE_ADDR)
Dcps.h506 #define GIC_SH_WEDGE 0x0280 macro
/ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/example_build/
Dcps.h506 #define GIC_SH_WEDGE 0x0280 macro
Dinit_gic.mip104 // (The actual interrupts are tied low and software sends interrupts via GIC_SH_WEDGE writes.)
Dstart.mip125 li k0, (GIC_SH_WEDGE | GIC_BASE_ADDR)