| /ThreadX-v6.3.0/ports/cortex_a8/ac6/ |
| D | readme_threadx.txt | 212 7.3 FIQ Interrupts
214 By default, FIQ interrupts are left alone by ThreadX. Of course, this
215 means that the application is fully responsible for enabling the FIQ interrupt
216 and saving/restoring any registers used in the FIQ ISR processing. To globally
217 enable FIQ interrupts, the application should enable FIQ interrupts at the
220 from default FIQ ISRs, which is located in tx_initialize_low_level.S.
223 7.3.1 Managed FIQ Interrupts
225 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
227 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
228 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a9/ac6/ |
| D | readme_threadx.txt | 215 7.3 FIQ Interrupts
217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
218 means that the application is fully responsible for enabling the FIQ interrupt
219 and saving/restoring any registers used in the FIQ ISR processing. To globally
220 enable FIQ interrupts, the application should enable FIQ interrupts at the
223 from default FIQ ISRs, which is located in tx_initialize_low_level.S.
226 7.3.1 Managed FIQ Interrupts
228 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
230 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
231 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_r5/ac6/ |
| D | readme_threadx.txt | 215 7.3 FIQ Interrupts
217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
218 means that the application is fully responsible for enabling the FIQ interrupt
219 and saving/restoring any registers used in the FIQ ISR processing. To globally
220 enable FIQ interrupts, the application should enable FIQ interrupts at the
223 from default FIQ ISRs, which is located in tx_initialize_low_level.S.
226 7.3.1 Managed FIQ Interrupts
228 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
230 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
231 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a15/ac6/ |
| D | readme_threadx.txt | 215 7.3 FIQ Interrupts
217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
218 means that the application is fully responsible for enabling the FIQ interrupt
219 and saving/restoring any registers used in the FIQ ISR processing. To globally
220 enable FIQ interrupts, the application should enable FIQ interrupts at the
223 from default FIQ ISRs, which is located in tx_initialize_low_level.S.
226 7.3.1 Managed FIQ Interrupts
228 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
230 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
231 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_a7/ac6/ |
| D | readme_threadx.txt | 215 7.3 FIQ Interrupts
217 By default, FIQ interrupts are left alone by ThreadX. Of course, this
218 means that the application is fully responsible for enabling the FIQ interrupt
219 and saving/restoring any registers used in the FIQ ISR processing. To globally
220 enable FIQ interrupts, the application should enable FIQ interrupts at the
223 from default FIQ ISRs, which is located in tx_initialize_low_level.S.
226 7.3.1 Managed FIQ Interrupts
228 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
230 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
231 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_r4/gnu/example_build/ |
| D | reset.S | 59 LDR pc, FIQ @ FIQ interrupt handler
75 FIQ: label
76 .word __tx_fiq_handler @ FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/cortex_r5/gnu/example_build/ |
| D | reset.S | 59 LDR pc, FIQ @ FIQ interrupt handler
75 FIQ: label
76 .word __tx_fiq_handler @ FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/arm11/gnu/example_build/ |
| D | reset.S | 59 LDR pc, FIQ @ FIQ interrupt handler
75 FIQ: label
76 .word __tx_fiq_handler @ FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/arm9/gnu/example_build/ |
| D | reset.S | 59 LDR pc, FIQ @ FIQ interrupt handler
75 FIQ: label
76 .word __tx_fiq_handler @ FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/arm11/ac5/example_build/ |
| D | tx_initialize_low_level.s | 35 SVC_MODE EQU 0xD3 ; Disable IRQ/FIQ SVC mode
36 IRQ_MODE EQU 0xD2 ; Disable IRQ/FIQ IRQ mode
37 FIQ_MODE EQU 0xD1 ; Disable IRQ/FIQ FIQ mode
38 SYS_MODE EQU 0xDF ; Disable IRQ/FIQ SYS mode
40 FIQ_STACK_SIZE EQU 512 ; FIQ stack size
55 FIQStatus EQU 0x0a000100 ; FIQ Status Register
56 FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register
57 FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register
58 FIQEnableClear EQU 0x0a00010C ; FIQ Enable Clear Register
60 TIMER1_BIT EQU 0x00000010 ; IRQ/FIQ Timer1 bit
[all …]
|
| /ThreadX-v6.3.0/ports/arm9/ac5/example_build/ |
| D | tx_initialize_low_level.s | 35 SVC_MODE EQU 0xD3 ; Disable IRQ/FIQ SVC mode
36 IRQ_MODE EQU 0xD2 ; Disable IRQ/FIQ IRQ mode
37 FIQ_MODE EQU 0xD1 ; Disable IRQ/FIQ FIQ mode
38 SYS_MODE EQU 0xDF ; Disable IRQ/FIQ SYS mode
40 FIQ_STACK_SIZE EQU 512 ; FIQ stack size
55 FIQStatus EQU 0x0a000100 ; FIQ Status Register
56 FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register
57 FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register
58 FIQEnableClear EQU 0x0a00010C ; FIQ Enable Clear Register
60 TIMER1_BIT EQU 0x00000010 ; IRQ/FIQ Timer1 bit
[all …]
|
| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/ |
| D | readme_threadx.txt | 222 6.3 FIQ Interrupts
224 By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this
225 means that the application is fully responsible for enabling the FIQ interrupt
226 and saving/restoring any registers used in the FIQ ISR processing. To globally
227 enable FIQ interrupts, the application should enable FIQ interrupts at the
230 from default FIQ ISRs, which is located in tx_initialize_low_level.s.
233 6.3.1 Managed FIQ Interrupts
235 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
237 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
238 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/ |
| D | readme_threadx.txt | 222 6.3 FIQ Interrupts
224 By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this
225 means that the application is fully responsible for enabling the FIQ interrupt
226 and saving/restoring any registers used in the FIQ ISR processing. To globally
227 enable FIQ interrupts, the application should enable FIQ interrupts at the
230 from default FIQ ISRs, which is located in tx_initialize_low_level.s.
233 6.3.1 Managed FIQ Interrupts
235 Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
237 this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
238 handlers defined previously. The following is default FIQ handler
[all …]
|
| /ThreadX-v6.3.0/ports/cortex_r4/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a8/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a9/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_r5/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_r7/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a7/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a5/ghs/src/ |
| D | tx_thread_fiq_nesting_start.arm | 34 FIQ_DISABLE = 0x40 # FIQ disable bit
54 /* This function is called by the application from FIQ mode after */
55 /* _tx_thread_fiq_context_save has been called and switches the FIQ */
56 /* processing to the system mode so nested FIQ interrupt processing */
61 /* This function returns with FIQ interrupts enabled. */
96 BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR
|
| /ThreadX-v6.3.0/ports/cortex_a8/ghs/example_build/ |
| D | reset.arm | 16 LDR pc,FIQ # FIQ interrupt handler
40 FIQ:
41 .data.w __tx_fiq_handler # FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/cortex_a9/ghs/example_build/ |
| D | reset.arm | 16 LDR pc,FIQ # FIQ interrupt handler
40 FIQ:
41 .data.w __tx_fiq_handler # FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/cortex_r5/ghs/example_build/ |
| D | reset.arm | 16 LDR pc,FIQ # FIQ interrupt handler
40 FIQ:
41 .data.w __tx_fiq_handler # FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/cortex_r7/ghs/example_build/ |
| D | reset.arm | 16 LDR pc,FIQ # FIQ interrupt handler
40 FIQ:
41 .data.w __tx_fiq_handler # FIQ interrupt handler
|
| /ThreadX-v6.3.0/ports/cortex_r4/ghs/example_build/ |
| D | reset.arm | 16 LDR pc,FIQ # FIQ interrupt handler
40 FIQ:
41 .data.w __tx_fiq_handler # FIQ interrupt handler
|
