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Searched refs:GICD_ICFGR (Results 1 – 25 of 66) sorted by relevance

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/ThreadX-v6.2.1/ports/cortex_a55/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a57/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a34/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a65/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a53/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a35/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a53/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a35/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a55/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a72/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a75/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a75/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports/cortex_a76/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_module/cortex_a35/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()
/ThreadX-v6.2.1/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c52 volatile uint32_t GICD_ICFGR[64]; // +0x0c00 member
218 bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); in ConfigureSPI()
223 tmp = gicd.GICD_ICFGR[bank]; in ConfigureSPI()
226 gicd.GICD_ICFGR[bank] = tmp; in ConfigureSPI()

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