| /ThreadX-v6.4.1/ports/cortex_m3/ghs/src/ |
| D | tx_timer_interrupt.arm | 152 LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start
153 LDR r0, [r3, #0] ; Set current pointer to list start
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx/ghs/src/ |
| D | tx_timer_interrupt.arm | 152 LDR r3, =_tx_timer_list_start // Pickup addr of timer list start
153 LDR r0, [r3, #0] // Set current pointer to list start
|
| /ThreadX-v6.4.1/ports/cortex_m4/ghs/src/ |
| D | tx_timer_interrupt.arm | 152 LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start
153 LDR r0, [r3, #0] ; Set current pointer to list start
|
| /ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 198 LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end
199 STRD r0, r1, [r2, #0x0C] ; Set stack start and end
236 LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end
237 STRD r0, r1, [r2, #0x0C] ; Set stack start and end
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/ |
| D | readme_threadx.txt | 83 E. To start execution, select and run Id 0, Id 4, and Id 8. All the cores are now
99 This is defined within the start.mip file supplied by MIPS. In addition,
112 By default, the first available RAM memory address is assumed to start at the
258 wait until VPE 0 completes the initialization before they start running.
|
| /ThreadX-v6.4.1/ports_module/cortex_r4/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 181 LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end
182 STRD r0, r1, [r2, #0x0C] ; Set stack start and end
217 LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end
218 STRD r0, r1, [r2, #0x0C] ; Set stack start and end
|
| /ThreadX-v6.4.1/ports/rxv1/ccrx/src/ |
| D | tx_timer_interrupt.src | 199 MOV.L #__tx_timer_list_start, R2 ; Pickup the timer list start ptr
200 MOV.L [R2], R2 ; Pickup the start of the list
|
| /ThreadX-v6.4.1/ports/rxv2/ccrx/src/ |
| D | tx_timer_interrupt.src | 199 MOV.L #__tx_timer_list_start, R2 ; Pickup the timer list start ptr
200 MOV.L [R2], R2 ; Pickup the start of the list
|
| /ThreadX-v6.4.1/ports/rxv3/ccrx/src/ |
| D | tx_timer_interrupt.src | 199 MOV.L #__tx_timer_list_start, R2 ; Pickup the timer list start ptr
200 MOV.L [R2], R2 ; Pickup the start of the list
|
| /ThreadX-v6.4.1/ports/cortex_m3/ghs/ |
| D | readme_threadx.txt | 66 By default, the first available RAM memory address is assumed to start at the
124 The Cortex-M3 vectors start at the label __tx_vectors. The application may modify
|
| /ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 204 LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end
205 STRD r0, r1, [r2, #0x0C] ; Set stack start and end
266 LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end
267 STRD r0, r1, [r2, #0x0C] ; Set stack start and end
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/iar/example_build/ |
| D | startup.s | 28 ; a user defined start symbol.
35 ; it is where the SP start value is found, and the NVIC vector
168 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/ |
| D | readme_threadx.txt | 58 This is defined within the start.S file supplied by MIPS. In addition,
71 By default, the first available RAM memory address is assumed to start at the
217 wait until VPE 0 completes the initialization before they start running.
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/iar/example_build/ |
| D | startup.s | 28 ; a user defined start symbol.
35 ; it is where the SP start value is found, and the NVIC vector
168 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/ |
| D | sample_threadx_module_manager.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/ |
| D | sample_threadx_module_manager.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/ |
| D | MP_SCU.s | 107 ; for the specified core. Typically only done at start-up.
|
| /ThreadX-v6.4.1/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | MP_SCU.s | 107 ; for the specified core. Typically only done at start-up.
|
| /ThreadX-v6.4.1/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/ |
| D | sample_threadx.ld | 132 /* gcc uses crtbegin.o to find the start of
|
