| /ThreadX-v6.4.1/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports/cortex_m3/ac5/example_build/ |
| D | tx_initialize_low_level.s | 183 ; Note: SVC must be lowest priority, which is 0xFF
187 ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/arc_hs/metaware/example_build/sample_threadx/ |
| D | tx_initialize_low_level.s | 128 mov r0, 15 ; Set timer 0 to priority 15
142 mov r0, 0 ; Set timer 1 to priority 0
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| /ThreadX-v6.4.1/ports/cortex_m3/keil/example_build/ |
| D | tx_initialize_low_level.s | 182 ; Note: SVC must be lowest priority, which is 0xFF
186 ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/ |
| D | tx_thread_smp_core_preempt.mip | 42 /* core must be used for a higher-priority thread. If the specified is */
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| /ThreadX-v6.4.1/ports/rxv3/ccrx/ |
| D | readme_threadx.txt | 30 typically setup for 10ms periodic interrupts and the interrupt priority level is set to
45 to perform context switch with the interrupt priority level 1. This ISR is thus reserved
166 priority 1 as this is the priority of the context switch interrupt. However using interrupt
167 priority 1 won't cause any negative side effects but doing so may slightly reduce
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| /ThreadX-v6.4.1/ports/cortex_m4/ac5/example_build/ |
| D | tx_initialize_low_level.s | 187 … ; Note: SVC must be lowest priority, which is 0xFF
191 … ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/cortex_m7/ac5/example_build/ |
| D | tx_initialize_low_level.s | 192 … ; Note: SVC must be lowest priority, which is 0xFF
196 … ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/cortex_m4/keil/example_build/ |
| D | tx_initialize_low_level.s | 202 … ; Note: SVC must be lowest priority, which is 0xFF
206 … ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports_module/cortex_m3/ac5/example_build/ |
| D | tx_initialize_low_level.S | 206 … ; Note: SVC must be lowest priority, which is 0xFF
210 … ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/src/ |
| D | tx_thread_smp_core_preempt.a64 | 51 /* core must be used for a higher-priority thread. If the specified is */
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| /ThreadX-v6.4.1/ports/rxv3/iar/src/ |
| D | tx_thread_schedule.s | 198 ; The priority of this interrupt is set to the lowest priority within
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| /ThreadX-v6.4.1/ports/rxv3/gnu/src/ |
| D | tx_thread_schedule.S | 202 ; The priority of this interrupt is set to the lowest priority within
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| /ThreadX-v6.4.1/utility/rtos_compatibility_layers/posix/ |
| D | px_int.h | 143 ULONG posix_priority_search(mqd_t msgQId ,ULONG priority);
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| /ThreadX-v6.4.1/ports/cortex_m0/ac5/example_build/ |
| D | tx_initialize_low_level.s | 196 … ; Note: SVC must be lowest priority, which is 0xFF
203 … ; Note: PnSV must be lowest priority, which is 0xFF
|
| /ThreadX-v6.4.1/ports/arc_em/metaware/example_build/sample_threadx/ |
| D | tx_initialize_low_level.s | 159 mov r0, 15 ; Set timer 0 to priority 15
173 mov r0, 2 ; Set timer 1 to priority 14
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| /ThreadX-v6.4.1/ports/cortex_m3/ghs/example_build/ |
| D | tx_initialize_low_level.arm | 122 ; Note: SVC must be lowest priority, which is 0xFF
126 ; Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/cortex_m0/keil/example_build/ |
| D | tx_initialize_low_level.s | 196 … ; Note: SVC must be lowest priority, which is 0xFF
203 … ; Note: PnSV must be lowest priority, which is 0xFF
|
