| /ThreadX-v6.4.1/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicr.c | 194 void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) in SetPrivateIntPriority() argument
203 gicrSGI->GICR_IPRIORITYR[id] = priority; in SetPrivateIntPriority()
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| /ThreadX-v6.4.1/ports/rxv1/ccrx/ |
| D | readme_threadx.txt | 30 typically setup for 10ms periodic interrupts and the interrupt priority level is set to
45 to perform context switch with the interrupt priority level 1. This ISR is thus reserved
107 priority 1 as this is the priority of the context switch interrupt. However using interrupt
108 priority 1 won't cause any negative side effects but doing so may slightly reduce
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| /ThreadX-v6.4.1/ports/rxv2/ccrx/ |
| D | readme_threadx.txt | 30 typically setup for 10ms periodic interrupts and the interrupt priority level is set to
45 to perform context switch with the interrupt priority level 1. This ISR is thus reserved
110 priority 1 as this is the priority of the context switch interrupt. However using interrupt
111 priority 1 won't cause any negative side effects but doing so may slightly reduce
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| /ThreadX-v6.4.1/ports/rxv2/gnu/ |
| D | readme_threadx.txt | 30 interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in
46 to perform context switch with the interrupt priority level 1. This ISR is thus reserved
110 priority 1 as this is the priority of the context switch interrupt. However using interrupt
111 priority 1 won't cause any negative side effects but doing so may slightly reduce
|
| /ThreadX-v6.4.1/ports/cortex_m3/ac6/example_build/sample_threadx/ |
| D | tx_initialize_low_level.S | 137 … @ Note: SVC must be lowest priority, which is 0xFF
141 … @ Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/cortex_m4/ac6/example_build/sample_threadx/ |
| D | tx_initialize_low_level.S | 137 … @ Note: SVC must be lowest priority, which is 0xFF
141 … @ Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/cortex_m7/ac6/example_build/sample_threadx/ |
| D | tx_initialize_low_level.S | 137 … @ Note: SVC must be lowest priority, which is 0xFF
141 … @ Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/ports/cortex_m4/gnu/example_build/ |
| D | tx_initialize_low_level.S | 143 … @ Note: SVC must be lowest priority, which is 0xFF
147 … @ Note: PnSV must be lowest priority, which is 0xFF
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| /ThreadX-v6.4.1/utility/rtos_compatibility_layers/posix/ |
| D | posix_demo.c | 233 ULONG priority; in pthread_2_entry() local
241 pt2_status = mq_receive(q_des,msgr0,MAX_MESSAGE_SIZE,&priority); in pthread_2_entry()
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| /ThreadX-v6.4.1/utility/rtos_compatibility_layers/FreeRTOS/ |
| D | readme.md | 32 …ended, but not required to have the timer task priority set at priority 0, which is the highest p…
114 …le task to perform the same duty. The idle task has the lowest possible priority allowed by Thread…
117 …priority task ready to run. As such the `taskYIELD_FROM_ISR()` macro has no effect and yielding wi…
145 …s in reverse orders since under FreeRTOS increasing priority values means an increasing task prior…
161 | taskYIELD_FROM_ISR() | Has no effect, ThreadX will automatically pre-empt when a higher priority …
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| /ThreadX-v6.4.1/ports/rxv3/gnu/ |
| D | readme_threadx.txt | 30 interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in
46 to perform context switch with the interrupt priority level 1. This ISR is thus reserved
164 priority 1 as this is the priority of the context switch interrupt. However using interrupt
165 priority 1 won't cause any negative side effects but doing so may slightly reduce
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| /ThreadX-v6.4.1/ports/rxv3/iar/ |
| D | readme_threadx.txt | 29 interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in
43 to perform context switch with the interrupt priority level 1. This ISR is thus reserved
164 priority 1 as this is the priority of the context switch interrupt. However using interrupt
165 priority 1 won't cause any negative side effectd but doing so may slightly reduce
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| /ThreadX-v6.4.1/test/tx/regression/ |
| D | threadx_thread_information_test.c | 58 UINT priority; in thread_0_entry() local
85 …status += tx_thread_info_get(&thread_0, &name, &state, &run_count, &priority, &preemption_threshol… in thread_0_entry()
88 … (state != TX_READY) || (run_count != thread_0.tx_thread_run_count) || (priority != 16) || (preemp… in thread_0_entry()
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| /ThreadX-v6.4.1/test/smp/regression/ |
| D | threadx_thread_information_test.c | 58 UINT priority; in thread_0_entry() local
85 …status += tx_thread_info_get(&thread_0, &name, &state, &run_count, &priority, &preemption_threshol… in thread_0_entry()
88 … (state != TX_READY) || (run_count != thread_0.tx_thread_run_count) || (priority != 16) || (preemp… in thread_0_entry()
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| /ThreadX-v6.4.1/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
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| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
| /ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx/ |
| D | GICv3_gicd.c | 134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
143 gicd.GICD_IPRIORITYR[bank] = priority; in SetSPIPriority()
|
