Searched refs:heap (Results 26 – 50 of 183) sorted by relevance
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| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | sample_threadx.sct | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in memory m…
22 ; App heap for all CPUs
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| /ThreadX-v6.4.1/ports/cortex_a9/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_a17/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_a12/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_a15/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_a8/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_a7/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_a5/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 10 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memo…
33 ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
| /ThreadX-v6.4.1/ports/cortex_m0/gnu/example_build/ |
| D | sample_threadx.ld | 108 .heap (COPY):
111 *(.heap)
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| /ThreadX-v6.4.1/ports/cortex_m7/gnu/example_build/ |
| D | sample_threadx.ld | 108 .heap (COPY):
111 *(.heap)
|
| /ThreadX-v6.4.1/ports/cortex_m3/gnu/example_build/ |
| D | sample_threadx.ld | 108 .heap (COPY):
111 *(.heap)
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx/gnu/example_build/ |
| D | sample_threadx.ld | 108 .heap (COPY):
111 *(.heap)
|
| /ThreadX-v6.4.1/ports/cortex_m4/gnu/example_build/ |
| D | sample_threadx.ld | 108 .heap (COPY):
111 *(.heap)
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a76/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a65ae/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a77/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a34/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a75/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a65/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a53/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a55/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
| /ThreadX-v6.4.1/ports/cortex_a57/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 19 ; All stacks and heap are aligned to a cache-line boundary
24 ; Separate heap - import symbol __use_two_region_memory
31 ; All stacks and heap are aligned to a cache-line boundary
|
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