Searched refs:heap (Results 101 – 125 of 183) sorted by relevance
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| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/ |
| D | sample_threadx.scat | 31 ; App heap for all CPUs
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| /ThreadX-v6.4.1/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ |
| D | ARMCM33_AC6.sct | 68 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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| /ThreadX-v6.4.1/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ |
| D | ARMCM23_ac6.sct | 71 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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| /ThreadX-v6.4.1/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ |
| D | ARMCM23_ac6.sct | 79 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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| /ThreadX-v6.4.1/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ |
| D | ARMCM33_AC6.sct | 69 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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| /ThreadX-v6.4.1/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ |
| D | ARMCM23_ac6.sct | 71 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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| /ThreadX-v6.4.1/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ |
| D | ARMCM33_AC6.sct | 68 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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| /ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/tgt/ |
| D | standalone_ram.ld | 57 .heap ALIGN(16) PAD(heap_reserve) : > .
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| D | standalone_romrun.ld | 46 .heap ALIGN(16) PAD(heap_reserve) : > .
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| /ThreadX-v6.4.1/ports/cortex_r4/ac5/example_build/ |
| D | tx_initialize_low_level.s | 145 LDR r2, =HEAP_SIZE ; Pickup the heap size
146 ADD r1, r2, r1 ; Setup heap limit
210 LDR r2, =HEAP_SIZE ; Pickup the heap size
211 ADD r2, r2, r0 ; Setup heap limit
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| /ThreadX-v6.4.1/ports/cortex_a8/ac5/example_build/ |
| D | tx_initialize_low_level.s | 145 LDR r2, =HEAP_SIZE ; Pickup the heap size
146 ADD r1, r2, r1 ; Setup heap limit
210 LDR r2, =HEAP_SIZE ; Pickup the heap size
211 ADD r2, r2, r0 ; Setup heap limit
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| /ThreadX-v6.4.1/ports/cortex_a5/ac5/example_build/ |
| D | tx_initialize_low_level.s | 145 LDR r2, =HEAP_SIZE ; Pickup the heap size
146 ADD r1, r2, r1 ; Setup heap limit
210 LDR r2, =HEAP_SIZE ; Pickup the heap size
211 ADD r2, r2, r0 ; Setup heap limit
|
| /ThreadX-v6.4.1/ports/cortex_r5/ac5/example_build/ |
| D | tx_initialize_low_level.s | 145 LDR r2, =HEAP_SIZE ; Pickup the heap size
146 ADD r1, r2, r1 ; Setup heap limit
210 LDR r2, =HEAP_SIZE ; Pickup the heap size
211 ADD r2, r2, r0 ; Setup heap limit
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| /ThreadX-v6.4.1/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/ |
| D | sample_threadx.cmd | 2 -heap 0x400
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| /ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/ |
| D | demo_threadx.ld | 53 ; App heap for all CPUs
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| /ThreadX-v6.4.1/ports/cortex_a9/ac5/example_build/ |
| D | tx_initialize_low_level.s | 165 LDR r2, =HEAP_SIZE ; Pickup the heap size
166 ADD r1, r2, r1 ; Setup heap limit
230 LDR r2, =HEAP_SIZE ; Pickup the heap size
231 ADD r2, r2, r0 ; Setup heap limit
|
| /ThreadX-v6.4.1/ports/cortex_a7/ac5/example_build/ |
| D | tx_initialize_low_level.s | 165 LDR r2, =HEAP_SIZE ; Pickup the heap size
166 ADD r1, r2, r1 ; Setup heap limit
230 LDR r2, =HEAP_SIZE ; Pickup the heap size
231 ADD r2, r2, r0 ; Setup heap limit
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| /ThreadX-v6.4.1/ports/c667x/ccs/example_build/sample_threadx_c6678evm/ |
| D | sample_threadx.cmd | 2 -heap 0x400
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| /ThreadX-v6.4.1/ports/cortex_m7/gnu/example_build/ |
| D | cortexm7_crt0.S | 90 .section .heap, "wa", %nobits
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| /ThreadX-v6.4.1/ports/cortex_m3/gnu/example_build/ |
| D | cortexm3_crt0.S | 90 .section .heap, "wa", %nobits
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| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx/gnu/example_build/ |
| D | cortexm4_crt0.S | 90 .section .heap, "wa", %nobits
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| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | demo_threadx_ram_interAptiv.ld | 61 .heap ALIGN(8) PAD(heap_reserve) : > .
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| /ThreadX-v6.4.1/ports/cortex_r5/ac6/example_build/sample_threadx/ |
| D | sample_threadx.scat | 26 ARM_LIB_STACKHEAP 0x48020000 EMPTY 0x4000 ; Stack and heap
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| /ThreadX-v6.4.1/ports/arm9/ac5/example_build/ |
| D | tx_initialize_low_level.s | 168 LDR r2, =HEAP_SIZE ; Pickup the heap size
169 ADD r1, r2, r1 ; Setup heap limit
247 LDR r2, =HEAP_SIZE ; Pickup the heap size
248 ADD r2, r2, r0 ; Setup heap limit
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| /ThreadX-v6.4.1/ports/arm11/ac5/example_build/ |
| D | tx_initialize_low_level.s | 168 LDR r2, =HEAP_SIZE ; Pickup the heap size
169 ADD r1, r2, r1 ; Setup heap limit
247 LDR r2, =HEAP_SIZE ; Pickup the heap size
248 ADD r2, r2, r0 ; Setup heap limit
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