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/ThreadX-v6.4.1/ports/cortex_a15/iar/src/
Dtx_thread_schedule.s150 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_fiq_context_restore.s115 BL _tx_execution_isr_exit ; Call the ISR exit function
Dtx_thread_schedule.s153 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_a7/iar/src/
Dtx_thread_fiq_context_restore.s115 BL _tx_execution_isr_exit ; Call the ISR exit function
Dtx_thread_schedule.s153 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_r5/ac5/src/
Dtx_thread_schedule.s149 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports_smp/cortex_a78_smp/ac6/src/
Dtx_thread_context_restore.S74 .type _tx_thread_context_restore, @function
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/
Dtx_thread_schedule.mip47 /* This function waits for a thread control block pointer to appear in */
65 /* _tx_initialize_kernel_enter ThreadX entry function */
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_schedule.s153 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_m0/ac5/example_build/
Dtx_initialize_low_level.s61 DCD Reset_Handler ; Reset goes to startup function
/ThreadX-v6.4.1/ports/cortex_r4/ac5/src/
Dtx_thread_schedule.s147 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_CoreFPGA6_mem.mip18 MIPS Technologies reserves the right to change this code to improve function, design or
Dinit_cpc.mip19 MIPS Technologies reserves the right to change this code to improve function, design or
Djoin_domain.mip19 MIPS Technologies reserves the right to change this code to improve function, design or
Dinit_tlb.mip19 MIPS Technologies reserves the right to change this code to improve function, design or
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_schedule.s153 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_a9/ac5/src/
Dtx_thread_schedule.s147 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_a8/ac5/src/
Dtx_thread_schedule.s147 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_a7/ac5/src/
Dtx_thread_schedule.s147 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports/cortex_m0/keil/example_build/
Dtx_initialize_low_level.s61 DCD Reset_Handler ; Reset goes to startup function
/ThreadX-v6.4.1/ports/cortex_a5/ac5/src/
Dtx_thread_schedule.s147 BL _tx_execution_thread_enter ; Call the thread execution enter function
/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
DMP_SCU.s164 ; This function invalidates the SCU copy of the tag rams
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_context_restore.s123 BL _tx_execution_isr_exit ; Call the ISR exit function
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
DMP_SCU.s164 ; This function invalidates the SCU copy of the tag rams
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_context_restore.s123 BL _tx_execution_isr_exit ; Call the ISR exit function

1...<<8182838485868788899091