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/ThreadX-v6.2.1/ports/xtensa/xcc/inc/
Dxtensa_rtos.h115 #define XT_INTS_DISABLE(reg) movi reg, PS_DI; xps reg, reg argument
116 #define XT_INTS_ENABLE(reg) wsr reg, PS; rsync argument
118 #define XT_INTS_DISABLE(reg) rsil reg, XCHAL_EXCM_LEVEL argument
119 #define XT_INTS_ENABLE(reg) wsr reg, PS; rsync argument