1//==================================================================
2// Copyright ARM Ltd 2012. All rights reserved.
3//
4// ARMv8 example - Startup Code
5//==================================================================
6
7  .section  BOOT,"ax"
8  .align 3
9
10// ------------------------------------------------------------
11
12.equ Mode_USR, 0x10
13
14.equ AArch32_Mode_USR,		 0x10
15.equ AArch32_Mode_FIQ,		 0x11
16.equ AArch32_Mode_IRQ,		 0x12
17.equ AArch32_Mode_SVC,		 0x13
18.equ AArch32_Mode_ABT,		 0x17
19.equ AArch32_Mode_UNDEF,   0x1B
20.equ AArch32_Mode_SYS,		 0x1F
21.equ AArch32_Mode_HYP,     0x1A
22.equ AArch32_Mode_MON,     0x16
23
24.equ AArch64_EL2_SP2,      0x09    // EL2h
25.equ AArch64_EL2_SP0,      0x08    // EL2t
26.equ AArch64_EL1_SP1,      0x05    // EL1h
27.equ AArch64_EL1_SP0,      0x04    // EL1t
28.equ AArch64_EL0_SP0,      0x00
29
30.equ AArch32_State_Thumb,  0x20
31.equ AArch32_State_ARM,    0x00
32
33// ------------------------------------------------------------
34
35.equ TT_S1_TABLE,          0x00000000000000003    // NSTable=0, PXNTable=0, UXNTable=0, APTable=0
36
37// TT block entries templates   (L1 and L2, NOT L3)
38// Assuming table contents:
39// 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
40// 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
41// 2 = b00000000 = Device-nGnRnE
42.equ TT_S1_FAULT,           0x0
43.equ TT_S1_NORMAL_NO_CACHE, 0x00000000000000401    // Index = 0, AF=1
44.equ TT_S1_NORMAL_WBWA,     0x00000000000000405    // Index = 1, AF=1
45.equ TT_S1_DEVICE_nGnRnE,   0x00000000000000409    // Index = 2, AF=1
46
47.equ TT_S1_UXN,             (1 << 54)
48.equ TT_S1_PXN,             (1 << 53)
49.equ TT_S1_nG,              (1 << 11)
50.equ TT_S1_NS,              (1 << 5)
51
52.equ TT_S1_NON_SHARED,      (0 << 8)               // Non-shareable
53.equ TT_S1_INNER_SHARED,    (3 << 8)               // Inner-shareable
54.equ TT_S1_OUTER_SHARED,    (2 << 8)               // Outer-shareable
55
56.equ TT_S1_PRIV_RW,         (0x0)
57.equ TT_S1_PRIV_RO,         (0x2 << 6)
58.equ TT_S1_USER_RW,         (0x1 << 6)
59.equ TT_S1_USER_RO,         (0x3 << 6)
60
61// ------------------------------------------------------------
62
63  .global start64
64  .type start64, @function
65start64:
66
67  // Clear registers
68  // ---------------
69  // This is primarily for RTL simulators, to avoid
70  // possibility of X propergation
71  MOV      x0, #0
72  MOV      x1, #0
73  MOV      x2, #0
74  MOV      x3, #0
75  MOV      x4, #0
76  MOV      x5, #0
77  MOV      x6, #0
78  MOV      x7, #0
79  MOV      x8, #0
80  MOV      x9, #0
81  MOV      x10, #0
82  MOV      x11, #0
83  MOV      x12, #0
84  MOV      x13, #0
85  MOV      x14, #0
86  MOV      x15, #0
87  MOV      x16, #0
88  MOV      x17, #0
89  MOV      x18, #0
90  MOV      x19, #0
91  MOV      x20, #0
92  MOV      x21, #0
93  MOV      x22, #0
94  MOV      x23, #0
95  MOV      x24, #0
96  MOV      x25, #0
97  MOV      x26, #0
98  MOV      x27, #0
99  MOV      x28, #0
100  MOV      x29, #0
101  MOV      x30, #0
102
103  // Which core am I
104  // ----------------
105  MRS      x0, MPIDR_EL1
106  AND      x0, x0, #0xFF                     // Mask off to leave Aff0
107  CBZ      x0, boot                          // If core 0, run the primary init code
108sleep:
109  WFI
110  B        sleep
111boot:
112
113
114  // Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU
115  // -------------------------------------------------------------
116  MOV      x0, #0                           // Clear all trap bits
117  MSR      CPTR_EL3, x0
118
119
120  // Install vector table
121  // ---------------------
122  LDR      x0, vector_table_address
123  MSR      VBAR_EL3, x0
124
125
126  // Configure SCR_EL3
127  // ------------------
128  MOV      w1, #0              // Initial value of register is unknown
129  ORR      w1, w1, #(1 << 11)  // Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
130  ORR      w1, w1, #(1 << 10)  // Set RW bit (EL1 is AArch64, as this is the Secure world)
131  ORR      w1, w1, #(1 << 3)   // Set EA bit (SError routed to EL3)
132  ORR      w1, w1, #(1 << 2)   // Set FIQ bit (FIQs routed to EL3)
133  ORR      w1, w1, #(1 << 1)   // Set IRQ bit (IRQs routed to EL3)
134  MSR      SCR_EL3, x1
135
136
137  //
138  // Cortex-A series specified configuration
139  //
140  .ifdef CORTEXA
141    // Configure ACTLR_EL1
142    // --------------------
143    // These bits are IMP DEF, so need to different for different
144    // processors
145    //MRS      x1, ACTLR_EL1
146    //ORR      x1, x1, #1          // Enable EL1 access to ACTLR_EL1
147    //ORR      x1, x1, #(1 << 1)   // Enable EL1 access to CPUECTLR_EL1
148    //ORR      x1, x1, #(1 << 4)   // Enable EL1 access to L2CTLR_EL1
149    //ORR      x1, x1, #(1 << 5)   // Enable EL1 access to L2ECTLR_EL1
150    //ORR      x1, x1, #(1 << 6)   // Enable EL1 access to L2ACTLR_EL1
151    //MSR      ACTLR_EL1, x1
152
153    // Configure CPUECTLR_EL1
154    // -----------------------
155    // These bits are IMP DEF, so need to different for different
156    // processors
157    // SMPEN - bit 6 - Enables the processor to receive cache
158    //                 and TLB maintenance operations
159    //
160    // NOTE: For Cortex-A57/53 CPUEN should be set beforebefore
161    //       enabling the caches and MMU, or performing any cache
162    //       and TLB maintenance operations.
163    //MRS      x0, S3_1_c15_c2_1  // Read EL1 CPU Extended Control Register
164    //ORR      x0, x0, #(1 << 6)  // Set the SMPEN bit
165    //MSR      S3_1_c15_c2_1, x0  // Write EL1 CPU Extended Control Register
166    //ISB
167  .endif
168
169
170  // Ensure changes to system register are visible before MMU enabled
171  ISB
172
173
174  // Enable Interrupts
175  // ------------------
176  MSR      DAIFClr, 0x3
177
178
179  // Branch to scatter loading and C library init code
180  .global  __main
181  B        __main
182
183//==================================================================
184// Manually created literals pool
185//==================================================================
186  .align 3
187
188lit_stackheap_limit:
189  .global  Image$$ARM_LIB_STACKHEAP$$ZI$$Limit   // Linker symbol from scatter file
190  .quad (Image$$ARM_LIB_STACKHEAP$$ZI$$Limit)
191
192vector_table_address:
193  .global  el3_vectors
194  .quad    el3_vectors
195
196// ------------------------------------------------------------
197// End of file
198// ------------------------------------------------------------
199
200