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Searched refs:UX_HCD_SIM_HOST_TD_DATA_PHASE (Results 1 – 6 of 6) sorted by relevance

/USBX-v6.2.1/common/core/src/
Dux_hcd_sim_host_request_interupt_transfer.c101 data_td -> ux_sim_host_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_interrupt_transfer()
Dux_hcd_sim_host_request_bulk_transfer.c147 data_td -> ux_sim_host_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_bulk_transfer()
Dux_hcd_sim_host_request_isochronous_transfer.c167 data_td -> ux_sim_host_iso_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_isochronous_transfer()
Dux_hcd_sim_host_request_control_transfer.c214 data_td -> ux_sim_host_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_control_transfer()
Dux_hcd_sim_host_transaction_schedule.c241 if (data_td -> ux_sim_host_td_status & UX_HCD_SIM_HOST_TD_DATA_PHASE) in _ux_hcd_sim_host_transaction_schedule()
/USBX-v6.2.1/common/core/inc/
Dux_hcd_sim_host.h197 #define UX_HCD_SIM_HOST_TD_DATA_PHASE 0x00020000 macro