Searched refs:UX_HCD_SIM_HOST_TD_DATA_PHASE (Results 1 – 6 of 6) sorted by relevance
100 data_td -> ux_sim_host_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_interrupt_transfer()
146 data_td -> ux_sim_host_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_bulk_transfer()
166 data_td -> ux_sim_host_iso_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_isochronous_transfer()
213 data_td -> ux_sim_host_td_status |= UX_HCD_SIM_HOST_TD_DATA_PHASE; in _ux_hcd_sim_host_request_control_transfer()
240 if (data_td -> ux_sim_host_td_status & UX_HCD_SIM_HOST_TD_DATA_PHASE) in _ux_hcd_sim_host_transaction_schedule()
196 #define UX_HCD_SIM_HOST_TD_DATA_PHASE 0x00020000 macro