Home
last modified time | relevance | path

Searched refs:UX_DATA_MEMORY_BARRIER (Results 1 – 9 of 9) sorted by relevance

/USBX-v6.2.1/common/usbx_host_controllers/src/
Dux_hcd_ehci_request_interrupt_transfer.c123 UX_DATA_MEMORY_BARRIER in _ux_hcd_ehci_request_interrupt_transfer()
Dux_hcd_ehci_request_bulk_transfer.c159 UX_DATA_MEMORY_BARRIER in _ux_hcd_ehci_request_bulk_transfer()
Dux_hcd_ehci_request_control_transfer.c209 UX_DATA_MEMORY_BARRIER in _ux_hcd_ehci_request_control_transfer()
Dux_hcd_ehci_hsisochronous_tds_process.c448 UX_DATA_MEMORY_BARRIER in _ux_hcd_ehci_hsisochronous_tds_process()
/USBX-v6.2.1/ports/arm9/gnu/inc/
Dux_port.h248 #define UX_DATA_MEMORY_BARRIER __asm__ __volatile__("MCR p15, 0, r0, c7, c10, 4"); macro
/USBX-v6.2.1/ports/arm9/iar/inc/
Dux_port.h255 #define UX_DATA_MEMORY_BARRIER __asm volatile("MCR p15, 0, r0, c7, c10, 4"); macro
/USBX-v6.2.1/ports/cortex_a7/gnu/inc/
Dux_port.h255 #define UX_DATA_MEMORY_BARRIER __asm__ __volatile__("DMB"); macro
/USBX-v6.2.1/ports/cortex_a7/iar/inc/
Dux_port.h255 #define UX_DATA_MEMORY_BARRIER __asm volatile("DMB"); macro
/USBX-v6.2.1/common/core/inc/
Dux_api.h247 #ifndef UX_DATA_MEMORY_BARRIER
248 #define UX_DATA_MEMORY_BARRIER macro