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/ThreadX-v6.4.1/ports/risc-v64/gnu/src/
Dtx_thread_stack_build.S141 LOAD t0, 4*REGBYTES(a0) // Pickup end of stack area
143 and t0, t0, t1 // Make sure 16-byte alignment
148 addi t0, t0, -65*REGBYTES
150 addi t0, t0, -32*REGBYTES // Allocate space for the stack frame
153 STORE t1, 0*REGBYTES(t0) // Place stack type on the top
154 STORE x0, 1*REGBYTES(t0) // Initial s11
155 STORE x0, 2*REGBYTES(t0) // Initial s10
156 STORE x0, 3*REGBYTES(t0) // Initial s9
157 STORE x0, 4*REGBYTES(t0) // Initial s8
158 STORE x0, 5*REGBYTES(t0) // Initial s7
[all …]
Dtx_thread_context_restore.S82 la t0, _tx_thread_system_state // Pickup addr of nested interrupt count
83 LOAD t1, 0(t0) // Pickup nested interrupt count
85 STORE t1, 0(t0) // Store new nested count
115 lw t0, 63*REGBYTES(sp) // Recover fcsr
116 csrw fcsr, t0 //
138 LOAD t0, 63*REGBYTES(sp) // Recover fcsr
139 csrw fcsr, t0 //
149 LOAD t0, 30*REGBYTES(sp) // Recover mepc
150 csrw mepc, t0 // Setup mepc
151 li t0, 0x1880 // Prepare MPIP
[all …]
Dtx_thread_interrupt_control.S70 csrr t0, mstatus
71 mv t1, t0 // Save original mstatus for return
76 and t0, t0, t2 // Isolate interrupt lockout bits
77 or t0, t0, a0 // Put new lockout bits in
78 csrw mstatus, t0
Dtx_thread_system_return.S92 csrr t0, fcsr
93 STORE t0, 27*REGBYTES(sp) // Store fcsr
107 csrr t0, fcsr
108 STORE t0, 27*REGBYTES(sp) // Store fcsr
125 csrr t0, mstatus // Pickup mstatus
126 STORE t0, 14*REGBYTES(sp) // Save mstatus
138 la t0, _tx_thread_current_ptr // Pickup address of pointer
139 LOAD t1, 0(t0) // Pickup current thread pointer
171 STORE x0, 0(t0) // Clear current thread pointer
Dtx_initialize_low_level.S73 sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer
75 la t0, __tx_free_memory_start // Pickup first free address
76 sd t0, _tx_initialize_unused_memory, t1 // Save unused memory address
Dtx_thread_schedule.S78 la t0, _tx_thread_execute_ptr // Pickup address of execute ptr
80 LOAD t1, 0(t0) // Pickup next thread to execute
93 la t0, _tx_thread_current_ptr // Pickup current thread pointer address
94 STORE t1, 0(t0) // Set current thread pointer
161 LOAD t0, 63*REGBYTES(sp) // Recover fcsr
162 csrw fcsr, t0 //
196 LOAD t0, 63*REGBYTES(sp) // Recover fcsr
201 LOAD t0, 30*REGBYTES(sp) // Recover mepc
202 csrw mepc, t0 // Store mepc
203 li t0, 0x1880 // Prepare MPIP
[all …]
Dtx_thread_context_save.S104 csrr t0, mepc // Load exception program counter
105 STORE t0, 30*REGBYTES(sp) // Save it on the stack
129 csrr t0, fcsr
130 STORE t0, 63*REGBYTES(sp) // Store fcsr
152 csrr t0, fcsr
153 STORE t0, 63*REGBYTES(sp) // Store fcsr
193 csrr t0, mepc // Load exception program counter
194 STORE t0, 30*REGBYTES(sp) // Save it on the stack
218 csrr t0, fcsr
219 STORE t0, 63*REGBYTES(sp) // Store fcsr
[all …]
/ThreadX-v6.4.1/ports/risc-v32/iar/src/
Dtx_thread_stack_build.s150 lw t0, 16(a0) ; Pickup end of stack area
152 and t0, t0, t1 ; Make sure 16-byte alignment
157 addi t0, t0, -260
159 addi t0, t0, -128 ; Allocate space for the stack frame
162 sw t1, 0(t0) ; Place stack type on the top
163 sw x0, 4(t0) ; Initial s11
164 sw x0, 8(t0) ; Initial s10
165 sw x0, 12(t0) ; Initial s9
166 sw x0, 16(t0) ; Initial s8
167 sw x0, 20(t0) ; Initial s7
[all …]
Dtx_thread_context_restore.s103 la t0, _tx_thread_system_state ; Pickup addr of nested interrupt count
104 lw t1, 0(t0) ; Pickup nested interrupt count
106 sw t1, 0(t0) ; Store new nested count
138 lw t0, 0xFC(sp) ; Recover fcsr
139 csrw fcsr, t0 ;
149 lw t0, 0x78(sp) ; Recover mepc
150 csrw mepc, t0 ; Setup mepc
151 li t0, 0x1880 ; Prepare MPIP
152 csrw mstatus, t0 ; Enable MPIP
155 lw x5, 0x4C(sp) ; Recover t0
[all …]
Dtx_thread_interrupt_control.s80 csrr t0, mstatus
81 mv t1, t0 ; Save original mstatus for return
86 and t0, t0, t2 ; Isolate interrupt lockout bits
87 or t0, t0, a0 ; Put new lockout bits in
88 csrw mstatus, t0
Dtx_thread_schedule.s97 la t0, _tx_thread_execute_ptr ; Pickup address of execute ptr
99 lw t1, 0(t0) ; Pickup next thread to execute
112 la t0, _tx_thread_current_ptr ; Pickup current thread pointer address
113 sw t1, 0(t0) ; Set current thread pointer
Dtx_thread_system_return.s112 csrr t0, fcsr
113 sw t0, 0x6C(sp) ; Store fcsr
131 csrr t0, mstatus ; Pickup mstatus
132 sw t0, 0x38(sp) ; Save mstatus
144 la t0, _tx_thread_current_ptr ; Pickup address of pointer
145 lw t1, 0(t0) ; Pickup current thread pointer
Dtx_timer_interrupt.s95 la t0, _tx_timer_system_clock ; Pickup address of system clock
96 lw t1, 0(t0) ; Pickup system clock
100 sw t1, 0(t0) ; Store new system clock
136 la t0, _tx_timer_current_ptr ; Pickup address of current ptr
137 lw t1, 0(t0) ; Pickup current pointer
165 sw t1, 0(t0) ; Store new timer pointer
173 sw t4, 0(t0) ; Store new timer pointer*/
Dtx_initialize_low_level.s93 sw sp, _tx_thread_system_stack_ptr, t0 ; Save system stack pointer
95 la t0, __tx_free_memory_start ; Pickup first free address
96 sw t0, _tx_initialize_unused_memory, t1 ; Save unused memory address
Dtx_thread_context_save.s91 sw x5, 0x4C(sp) ; First store t0 and t1
122 csrr t0, mepc ; Load exception program counter
123 sw t0, 0x78(sp) ; Save it on the stack
149 csrr t0, fcsr
150 sw t0, 0xFC(sp) ; Store fcsr
190 csrr t0, mepc ; Load exception program counter
191 sw t0, 0x78(sp) ; Save it on the stack
217 csrr t0, fcsr
218 sw t0, 0xFC(sp) ; Store fcsr
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dregdef.h12 #define t0 $8 macro
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dregdef.h12 #define t0 $8 macro
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/
Dtx_thread_stack_build.mip97 $8 (84) Initial t0
183 sw $0, 84($8) # Initial t0
276 /* thread_ptr -> tx_thread_stack_ptr = t0; */
Dtx_thread_context_restore.mip155 lw $8, 84($29) # Recover t0
273 lw $8, 84($29) # Recover t0
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_stack_build.S179 sw $0, 84($8) # Initial t0
Dtx_thread_context_restore.S155 lw $8, 84($29) # Recover t0
Dtx_thread_context_save.S83 sw $8, 84($29) # Save t0
/ThreadX-v6.4.1/ports/risc-v32/iar/
Dreadme_threadx.txt51 The IAR RISC-V compiler assumes that registers t0-t6 and a0-a7 are scratch
87 0x4C t0 (x5) fs4
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/
Dreadme_threadx.txt85 The GNU MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25)
123 0x054 t0 ($8) |
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/
Dreadme_threadx.txt126 The Green Hills MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25)
164 0x054 t0 ($8) |

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