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/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_smp_initialize_wait.s81 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
82 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
83 LSL r10, r10, #2 // Build offset to array indexes
89 ADD r3, r3, r10 // Build index into the system state array
110 ADD r3, r3, r10 // Build index into the system state array
Dtx_thread_context_save.s89 STMDB sp!, {r0, r10, r12, lr} // Store other registers
97 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
98 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
99 LSL r12, r10, #2 // Build offset to array indexes
114 MOV r10, #0 // Clear stack limit
149 MOV r10, #0 // Clear stack limit
173 MOV r10, #0 // Clear stack limit
Dtx_thread_context_restore.s108 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
109 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
110 LSL r12, r10, #2 // Build offset to array indexes
129 LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
150 … CMP r2, r10 // Is the owning core the same as the protected core?
174 LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
184 LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers
198 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
199 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
200 LSL r12, r10, #2 // Build offset to array indexes
Dtx_thread_vectored_context_save.s87 MRC p15, 0, r10, c0, c0, 5 // Read CPU ID register
88 AND r10, r10, #0x03 // Mask off, leaving the CPU ID field
89 LSL r12, r10, #2 // Build offset to array indexes
106 MOV r10, #0 // Clear stack limit
147 MOV r10, #0 // Clear stack limit
175 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a9/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a15/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a17/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a12/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a8/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a5/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a7/gnu/example_build/
Dv7.s77 MOV r10, #0
80 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
85 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
100 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
109 ADD r10, r10, #2 // increment the cache number
110 CMP r3, r10
133 MOV r10, #0
136 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
141 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
156 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/example_build/
Dv7.S89 MOV r10, #0
92 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
97 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
112 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
121 ADD r10, r10, #2 // increment the cache number
122 CMP r3, r10
147 MOV r10, #0
150 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
155 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
170 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/example_build/
Dv7.S89 MOV r10, #0
92 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
97 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
112 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
121 ADD r10, r10, #2 // increment the cache number
122 CMP r3, r10
147 MOV r10, #0
150 ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel
155 MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register
170 ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11
[all …]
/ThreadX-v6.4.1/ports/cortex_a9/gnu/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a9/ac6/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a15/gnu/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a17/ac6/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a17/gnu/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a12/ac6/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a12/gnu/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a15/ac6/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a8/ac6/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit
/ThreadX-v6.4.1/ports/cortex_a8/gnu/src/
Dtx_thread_context_save.S120 PUSH {r0, r10, r12, lr} // Store other registers
124 MOV r10, #0 // Clear stack limit
152 PUSH {r2, r10, r12, lr} // Store other registers
154 MOV r10, #0 // Clear stack limit
174 MOV r10, #0 // Clear stack limit

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