| /ThreadX-v6.4.1/ports/cortex_a8/gnu/example_build/ |
| D | MP_GIC.s | 35 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
36 ORR r1, r1, #0x01 // Set bit 0, the enable bit
37 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
52 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
53 BIC r1, r1, #0x01 // Clear bit 0, the enable bit
54 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
67 MOV r1, r0 // Back up passed in ID value
73 MOV r2, r1 // Make working copy of ID in r2
79 AND r1, r1, #0x1F // Mask off to give offset within 32-bit block
81 MOV r3, r3, LSL r1 // Shift it left to position of ID
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a7/gnu/example_build/ |
| D | MP_GIC.s | 35 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
36 ORR r1, r1, #0x01 // Set bit 0, the enable bit
37 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
52 LDR r1, [r0] // Read the GIC Enable Register (ICDDCR)
53 BIC r1, r1, #0x01 // Clear bit 0, the enable bit
54 STR r1, [r0] // Write the GIC Enable Register (ICDDCR)
67 MOV r1, r0 // Back up passed in ID value
73 MOV r2, r1 // Make working copy of ID in r2
79 AND r1, r1, #0x1F // Mask off to give offset within 32-bit block
81 MOV r3, r3, LSL r1 // Shift it left to position of ID
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m23/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 91 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
92 STR r1, [r0] //
99 LDR r1, =0xE000ED04 // Load ICSR address
100 STR r0, [r1] // Set PENDSVBIT in ICSR
126 LDR r1, [r0] // Pickup the current thread pointer
127 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
129 LDR r1, [r0] // Pickup SHCSR
130 STR r1, [r2, #8] // Save SHCSR
132 LDR r1, [r0] // Pickup CFSR
133 STR r1, [r2, #12] // Save CFSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m23/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 95 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
96 STR r1, [r0] //
103 LDR r1, =0xE000ED04 // Load ICSR address
104 STR r0, [r1] // Set PENDSVBIT in ICSR
130 LDR r1, [r0] // Pickup the current thread pointer
131 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
133 LDR r1, [r0] // Pickup SHCSR
134 STR r1, [r2, #8] // Save SHCSR
136 LDR r1, [r0] // Pickup CFSR
137 STR r1, [r2, #12] // Save CFSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m23/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 101 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
102 STR r1, [r0] //
109 LDR r1, =0xE000ED04 // Load ICSR address
110 STR r0, [r1] // Set PENDSVBIT in ICSR
134 LDR r1, [r0] // Pickup the current thread pointer
135 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
137 LDR r1, [r0] // Pickup SHCSR
138 STR r1, [r2, #8] // Save SHCSR
140 LDR r1, [r0] // Pickup CFSR
141 STR r1, [r2, #12] // Save CFSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/iar/example_build/ |
| D | tx_initialize_low_level.s | 104 LDR r1, =__tx_free_memory_start // Build first free address
105 ADDS r1, r1, #4 //
106 STR r1, [r0] // Setup first unused memory pointer
111 LDR r1, =__vector_table // Pickup address of vector table
112 STR r1, [r0] // Set vector table address
117 LDR r1, =__vector_table // Pickup address of vector table
118 LDR r1, [r1] // Pickup reset stack pointer
119 STR r1, [r0] // Save system stack pointer
124 LDR r1, [r0] // Pickup the current value
126 ORRS r1, r1, r2 // Set the CYCCNTENA bit
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 98 LDR r1, =0xE000ED04 // Load ICSR address
99 STR r0, [r1] // Set PENDSVBIT in ICSR
130 LDR r1, [r0] // Pickup the current thread pointer
131 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
134 MRS r1, PSP // Pickup thread stack pointer
135 STR r1, [r2, #28] // Save thread stack pointer
136 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
138 LDR r0, [r1, #4] // Pickup saved r1
140 LDR r0, [r1, #8] // Pickup saved r2
155 LDR r0, [r1, #16] // Pickup saved r12
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 98 LDR r1, =0xE000ED04 // Load ICSR address
99 STR r0, [r1] // Set PENDSVBIT in ICSR
130 LDR r1, [r0] // Pickup the current thread pointer
131 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
134 MRS r1, PSP // Pickup thread stack pointer
135 STR r1, [r2, #28] // Save thread stack pointer
136 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
138 LDR r0, [r1, #4] // Pickup saved r1
140 LDR r0, [r1, #8] // Pickup saved r2
155 LDR r0, [r1, #16] // Pickup saved r12
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/iar/module_manager/src/ |
| D | tx_thread_schedule.S | 99 LDR r1, =0xE000ED04 // Load ICSR address
100 STR r0, [r1] // Set PENDSVBIT in ICSR
122 LDR r1, [r0] // Pickup the current thread pointer
123 …STR r1, [r2, #0] // Save current thread pointer in fault info struc…
126 MRS r1, PSP // Pickup thread stack pointer
127 STR r1, [r2, #28] // Save thread stack pointer
128 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
130 LDR r0, [r1, #4] // Pickup saved r1
132 LDR r0, [r1, #8] // Pickup saved r2
147 LDR r0, [r1, #16] // Pickup saved r12
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 107 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
108 STR r1, [r0] //
116 MOV r1, #0xE000E000 // Load NVIC base
117 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 111 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
112 STR r1, [r0] //
120 MOV r1, #0xE000E000 // Load NVIC base
121 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 107 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
108 STR r1, [r0] //
116 MOV r1, #0xE000E000 // Load NVIC base
117 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 111 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
112 STR r1, [r0] //
120 MOV r1, #0xE000E000 // Load NVIC base
121 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 111 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
112 STR r1, [r0] //
120 MOV r1, #0xE000E000 // Load NVIC base
121 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 113 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
114 STR r1, [r0] //
122 MOV r1, #0xE000E000 // Load NVIC base
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
147 MSR BASEPRI, r1
156 LDR r1, [r0] // Pickup the current thread pointer
157 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
159 LDR r1, [r0] // Pickup SHCSR
160 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 107 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
108 STR r1, [r0] //
116 MOV r1, #0xE000E000 // Load NVIC base
117 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 107 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
108 STR r1, [r0] //
116 MOV r1, #0xE000E000 // Load NVIC base
117 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 111 LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults
112 STR r1, [r0] //
120 MOV r1, #0xE000E000 // Load NVIC base
121 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
137 LDR r1, =TX_PORT_BASEPRI // Mask interrupt priorities =< TX_PORT_BASEPRI
138 MSR BASEPRI, r1
147 LDR r1, [r0] // Pickup the current thread pointer
148 …STR r1, [r12, #0] // Save current thread pointer in fault info struc…
150 LDR r1, [r0] // Pickup SHCSR
151 STR r1, [r12, #8] // Save SHCSR
[all …]
|
