| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/example_build/ |
| D | MP_SCU.S | 26 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
28 LDR r0, [r0, #0x004] // Read SCU Configuration register
29 AND r0, r0, #0x3 // Bits 1:0 gives the number of cores-1
30 ADD r0, r0, #1
46 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
48 LDR r1, [r0, #0x0] // Read the SCU Control Register
50 STR r1, [r0, #0x0] // Write back modifed value
66 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
68 LDR r0, [r0, #0x004] // Read SCU Configuration register
69 MOV r0, r0, LSR #4 // Bits 7:4 gives the cores in SMP mode, shift then mask
[all …]
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/example_build/ |
| D | MP_SCU.S | 26 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
28 LDR r0, [r0, #0x004] // Read SCU Configuration register
29 AND r0, r0, #0x3 // Bits 1:0 gives the number of cores-1
30 ADD r0, r0, #1
46 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
48 LDR r1, [r0, #0x0] // Read the SCU Control Register
50 STR r1, [r0, #0x0] // Write back modifed value
66 MRC p15, 4, r0, c15, c0, 0 // Read periph base address
68 LDR r0, [r0, #0x004] // Read SCU Configuration register
69 MOV r0, r0, LSR #4 // Bits 7:4 gives the cores in SMP mode, shift then mask
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m23/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 85 MOVW r0, #0 // Build value for TX_FALSE
87 STR r0, [r2, #0] // Clear preempt disable flag
90 LDR r0, =0xE000ED24 // Build SHCSR address
92 STR r1, [r0] //
98 LDR r0, =0x10000000 // Load PENDSVSET bit
100 STR r0, [r1] // Set PENDSVBIT in ICSR
125 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
126 LDR r1, [r0] // Pickup the current thread pointer
128 LDR r0, =0xE000ED24 // Build SHCSR address
129 LDR r1, [r0] // Pickup SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m23/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 89 MOVW r0, #0 // Build value for TX_FALSE
91 STR r0, [r2, #0] // Clear preempt disable flag
94 LDR r0, =0xE000ED24 // Build SHCSR address
96 STR r1, [r0] //
102 LDR r0, =0x10000000 // Load PENDSVSET bit
104 STR r0, [r1] // Set PENDSVBIT in ICSR
129 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
130 LDR r1, [r0] // Pickup the current thread pointer
132 LDR r0, =0xE000ED24 // Build SHCSR address
133 LDR r1, [r0] // Pickup SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m23/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 95 MOVW r0, #0 // Build value for TX_FALSE
97 STR r0, [r2, #0] // Clear preempt disable flag
100 LDR r0, =0xE000ED24 // Build SHCSR address
102 STR r1, [r0] //
108 LDR r0, =0x10000000 // Load PENDSVSET bit
110 STR r0, [r1] // Set PENDSVBIT in ICSR
133 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
134 LDR r1, [r0] // Pickup the current thread pointer
136 LDR r0, =0xE000ED24 // Build SHCSR address
137 LDR r1, [r0] // Pickup SHCSR
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a9/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a17/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a12/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a15/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a8/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a7/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_a5/ac6/example_build/sample_threadx/ |
| D | startup.S | 101 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
102 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
103 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
104 BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU
105 BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
106 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
116 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
117 ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit
118 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
126 MOV r0,#0
[all …]
|
| /ThreadX-v6.4.1/ports/cortex_r4/ac6/example_build/sample_threadx/ |
| D | startup.S | 69 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
70 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
71 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
72 BIC r0, r0, #0x1 // Clear M bit 0 to disable MPU
74 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
85 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
86 ORR r0, r0, #(0x1 << 17) // Enable RSDIS bit 17 to disable the return stack
87 ORR r0, r0, #(0x1 << 16) // Clear BP bit 15 and set BP bit 16:
88 … BIC r0, r0, #(0x1 << 15) // Branch always not taken and history table updates disabled
89 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/ |
| D | startup.S | 69 MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
70 BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
71 BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
72 BIC r0, r0, #0x1 // Clear M bit 0 to disable MPU
74 MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
85 MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
86 ORR r0, r0, #(0x1 << 17) // Enable RSDIS bit 17 to disable the return stack
87 ORR r0, r0, #(0x1 << 16) // Clear BP bit 15 and set BP bit 16:
88 … BIC r0, r0, #(0x1 << 15) // Branch always not taken and history table updates disabled
89 MCR p15, 0, r0, c1, c0, 1 // Write ACTLR
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 89 MOVS r0, #0 // Build value for TX_FALSE
91 STR r0, [r2, #0] // Clear preempt disable flag
97 LDR r0, =0x10000000 // Load PENDSVSET bit
99 STR r0, [r1] // Set PENDSVBIT in ICSR
129 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
130 LDR r1, [r0] // Pickup the current thread pointer
132 MRS r0, CONTROL // Pickup current CONTROL register
133 STR r0, [r2, #24] // Save CONTROL
136 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
137 STR r0, [r2, #32] // Save r0
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 89 MOVS r0, #0 // Build value for TX_FALSE
91 STR r0, [r2, #0] // Clear preempt disable flag
97 LDR r0, =0x10000000 // Load PENDSVSET bit
99 STR r0, [r1] // Set PENDSVBIT in ICSR
129 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
130 LDR r1, [r0] // Pickup the current thread pointer
132 MRS r0, CONTROL // Pickup current CONTROL register
133 STR r0, [r2, #24] // Save CONTROL
136 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
137 STR r0, [r2, #32] // Save r0
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m0+/iar/module_manager/src/ |
| D | tx_thread_schedule.S | 90 MOVS r0, #0 // Build value for TX_FALSE
92 STR r0, [r2, #0] // Clear preempt disable flag
98 LDR r0, =0x10000000 // Load PENDSVSET bit
100 STR r0, [r1] // Set PENDSVBIT in ICSR
121 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
122 LDR r1, [r0] // Pickup the current thread pointer
124 MRS r0, CONTROL // Pickup current CONTROL register
125 STR r0, [r2, #24] // Save CONTROL
128 …LDR r0, [r1] // Pickup saved r0 (as r0-r3, r12, lr, pc, xpsr ar…
129 STR r0, [r2, #32] // Save r0
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 100 MOV r0, #0 // Build value for TX_FALSE
102 STR r0, [r2, #0] // Clear preempt disable flag
106 MRS r0, CONTROL // Pickup current CONTROL register
107 BIC r0, r0, #4 // Clear the FPCA bit
108 MSR CONTROL, r0 // Setup new CONTROL register
112 LDR r0, =0xE000ED24 // Build SHCSR address
114 STR r1, [r0] //
121 MOV r0, #0x10000000 // Load PENDSVSET bit
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
155 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 100 MOV r0, #0 // Build value for TX_FALSE
102 STR r0, [r2, #0] // Clear preempt disable flag
106 MRS r0, CONTROL // Pickup current CONTROL register
107 BIC r0, r0, #4 // Clear the FPCA bit
108 MSR CONTROL, r0 // Setup new CONTROL register
112 LDR r0, =0xE000ED24 // Build SHCSR address
114 STR r1, [r0] //
121 MOV r0, #0x10000000 // Load PENDSVSET bit
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
155 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m7/iar/module_manager/src/ |
| D | tx_thread_schedule.s | 94 MOV r0, #0 // Build value for TX_FALSE
96 STR r0, [r2, #0] // Clear preempt disable flag
100 MRS r0, CONTROL // Pickup current CONTROL register
101 BIC r0, r0, #4 // Clear the FPCA bit
102 MSR CONTROL, r0 // Setup new CONTROL register
106 LDR r0, =0xE000ED24 // Build SHCSR address
108 STR r1, [r0] //
115 MOV r0, #0x10000000 // Load PENDSVSET bit
117 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m3/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 100 MOV r0, #0 // Build value for TX_FALSE
102 STR r0, [r2, #0] // Clear preempt disable flag
106 MRS r0, CONTROL // Pickup current CONTROL register
107 BIC r0, r0, #4 // Clear the FPCA bit
108 MSR CONTROL, r0 // Setup new CONTROL register
112 LDR r0, =0xE000ED24 // Build SHCSR address
114 STR r1, [r0] //
121 MOV r0, #0x10000000 // Load PENDSVSET bit
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
155 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/ac5/module_manager/src/ |
| D | tx_thread_schedule.s | 98 MOV r0, #0 // Build value for TX_FALSE
100 STR r0, [r2, #0] // Clear preempt disable flag
104 MRS r0, CONTROL // Pickup current CONTROL register
105 BIC r0, r0, #4 // Clear the FPCA bit
106 MSR CONTROL, r0 // Setup new CONTROL register
110 LDR r0, =0xE000ED24 // Build SHCSR address
112 STR r1, [r0] //
119 MOV r0, #0x10000000 // Load PENDSVSET bit
121 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
146 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/ac6/module_manager/src/ |
| D | tx_thread_schedule.S | 100 MOV r0, #0 // Build value for TX_FALSE
102 STR r0, [r2, #0] // Clear preempt disable flag
106 MRS r0, CONTROL // Pickup current CONTROL register
107 BIC r0, r0, #4 // Clear the FPCA bit
108 MSR CONTROL, r0 // Setup new CONTROL register
112 LDR r0, =0xE000ED24 // Build SHCSR address
114 STR r1, [r0] //
121 MOV r0, #0x10000000 // Load PENDSVSET bit
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
155 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
| /ThreadX-v6.4.1/ports_module/cortex_m4/gnu/module_manager/src/ |
| D | tx_thread_schedule.S | 100 MOV r0, #0 // Build value for TX_FALSE
102 STR r0, [r2, #0] // Clear preempt disable flag
106 MRS r0, CONTROL // Pickup current CONTROL register
107 BIC r0, r0, #4 // Clear the FPCA bit
108 MSR CONTROL, r0 // Setup new CONTROL register
112 LDR r0, =0xE000ED24 // Build SHCSR address
114 STR r1, [r0] //
121 MOV r0, #0x10000000 // Load PENDSVSET bit
123 STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
155 LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
[all …]
|
