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Searched refs:pad (Results 1 – 22 of 22) sorted by relevance

/ThreadX-v6.4.1/ports/cortex_m3/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
45 .sys_regs 0xE0000000 pad(0xe000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
44 .sys_regs 0xE0000000 pad(0xe000) :
/ThreadX-v6.4.1/ports/cortex_m4/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
45 .sys_regs 0xE0000000 pad(0xe000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
44 .sys_regs 0xE0000000 pad(0xe000) :
/ThreadX-v6.4.1/ports/cortex_m7/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
45 .sys_regs 0xE0000000 pad(0xe000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
44 .sys_regs 0xE0000000 pad(0xe000) :
/ThreadX-v6.4.1/ports/cortex_a9/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports/cortex_r4/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports/cortex_r5/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports/cortex_r7/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports/cortex_a8/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports/cortex_a5/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports/cortex_a7/ghs/example_build/
Dsample_threadx_el.ld41 .heap align(16) pad(0x1000) :
42 .stack align(16) pad(0x1000) :
43 .eventlog align(16) pad(0x10000) :
44 .free_mem align(16) pad(0x10000) :
Dsample_threadx.ld41 .heap align(16) pad(0x10000) :
42 .stack align(16) pad(0x1000) :
43 .free_mem align(16) pad(0x10000) :
/ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/
Darc.c116 unsigned int cmd:8, param:16, pad:8; in __mcip_cmd() member
119 buf.pad = 0; in __mcip_cmd()
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Ddemo_threadx_ram_interAptiv.ld63 .eventlog align(16) pad(0x10000) :
64 .free_mem align(16) pad(0x10000) :