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/ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/
Dvectors.s8 .long _start ; exception 0 program entry point offset 0x0 0
9 .long _tx_memory_error ; exception 1 memory_error offset 0x4 4
10 .long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8
11 .long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12
12 .long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16
13 .long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20
14 .long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24
15 .long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28
16 .long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32
17 .long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36
[all …]
/ThreadX-v6.4.1/ports/arc_hs/metaware/example_build/sample_threadx/
Dvectors.s8 .long _start ; exception 0 program entry point offset 0x0 0
9 .long _tx_memory_error ; exception 1 memory_error offset 0x4 4
10 .long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8
11 .long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12
12 .long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16
13 .long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20
14 .long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24
15 .long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28
16 .long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32
17 .long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36
[all …]
/ThreadX-v6.4.1/ports/arc_em/metaware/example_build/sample_threadx/
Dvectors.s8 .long _start ; exception 0 program entry point offset 0x0 0
9 .long _tx_memory_error ; exception 1 memory_error offset 0x4 4
10 .long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8
11 .long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12
12 .long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16
13 .long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20
14 .long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24
15 .long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28
16 .long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32
17 .long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/example_build/
DMP_GIC.S13 @ ; Interrupt Distributor offset from base of private peripheral space --> 0x1000
14 @ ; CPU Interface offset from base of private peripheral space --> 0x2000
/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
DMP_GIC.S15 ; CPU Interface offset from base of private peripheral space --> 0x0100
16 ; Interrupt Distributor offset from base of private peripheral space --> 0x1000
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
DMP_GIC.s15 ; CPU Interface offset from base of private peripheral space --> 0x0100
16 ; Interrupt Distributor offset from base of private peripheral space --> 0x1000
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/
DMP_GIC.s18 ; CPU Interface offset from base of private peripheral space --> 0x0100
19 ; Interrupt Distributor offset from base of private peripheral space --> 0x1000
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/
DMP_GIC.s18 ; CPU Interface offset from base of private peripheral space --> 0x0100
19 ; Interrupt Distributor offset from base of private peripheral space --> 0x1000
/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c38 #define GIC_REG(offset) *((volatile uint32_t *)(GIC_BASEADDR+offset)) argument
54 #define GIC_CPU_REG(offset) *((volatile uint32_t *)(GIC_CPU_BASEADDR+offset)) argument
/ThreadX-v6.4.1/ports/cortex_a5x/ac6/example_build/sample_threadx/
Darmv8_aarch64_SystemTimer.h178 void setVirtualCounterOffset(unsigned long long offset);
/ThreadX-v6.4.1/ports/cortex_m55/ac6/example_build/
DCS300_config.txt12 … # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset
13 … # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_schedule.S103 LSL r12, r10, #2 @ Build offset to array indexes
106 ADD r1, r1, r12 @ Build offset to execute ptr for this core
130 MOV r2, #172 @ Build offset to the lock
277 LSL r1, r1, #2 @ Build offset to array indexes
299 LSL r1, r1, #2 @ Build offset to array indexes
Dtx_thread_smp_current_state_get.S91 LSL r2, r2, #2 @ Build offset to array indexes
Dtx_thread_smp_current_thread_get.S91 LSL r2, r2, #2 @ Build offset to array indexes
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/src/
Dtx_thread_schedule.S103 LSL r12, r10, #2 @ Build offset to array indexes
106 ADD r1, r1, r12 @ Build offset to execute ptr for this core
131 MOV r2, #172 @ Build offset to the lock
277 LSL r1, r1, #2 @ Build offset to array indexes
299 LSL r1, r1, #2 @ Build offset to array indexes
Dtx_thread_smp_current_state_get.S91 LSL r2, r2, #2 @ Build offset to array indexes
Dtx_thread_smp_current_thread_get.S91 LSL r2, r2, #2 @ Build offset to array indexes
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_schedule.s101 LSL r12, r10, #2 ; Build offset to array indexes
104 ADD r1, r1, r12 ; Build offset to execute ptr for this core
128 MOV r2, #172 ; Build offset to the lock
275 LSL r1, r1, #2 ; Build offset to array indexes
297 LSL r1, r1, #2 ; Build offset to array indexes
Dtx_thread_smp_current_state_get.s89 LSL r2, r2, #2 ; Build offset to array indexes
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_schedule.s101 LSL r12, r10, #2 ; Build offset to array indexes
104 ADD r1, r1, r12 ; Build offset to execute ptr for this core
129 MOV r2, #172 ; Build offset to the lock
275 LSL r1, r1, #2 ; Build offset to array indexes
297 LSL r1, r1, #2 ; Build offset to array indexes
Dtx_thread_smp_current_state_get.s89 LSL r2, r2, #2 ; Build offset to array indexes
Dtx_thread_smp_current_thread_get.s89 LSL r2, r2, #2 ; Build offset to array indexes
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_schedule.s101 LSL r12, r10, #2 ; Build offset to array indexes
104 ADD r1, r1, r12 ; Build offset to execute ptr for this core
128 MOV r2, #172 ; Build offset to the lock
275 LSL r1, r1, #2 ; Build offset to array indexes
297 LSL r1, r1, #2 ; Build offset to array indexes
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/src/
Dtx_thread_smp_current_state_get.S91 LSL r2, r2, #2 @ Build offset to array indexes
Dtx_thread_smp_current_thread_get.S91 LSL r2, r2, #2 @ Build offset to array indexes

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