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/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
Dv7.S62 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
65 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
71 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
72 ORR r11, r11, r7, LSL r2 ; factor in the index number
74 SUBS r9, r9, #1 ; decrement the way number
80 ADD r10, r10, #2 ; increment the cache number
117 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
120 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
126 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
127 ORR r11, r11, r7, LSL r2 ; factor in the index number
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
Dv7.s62 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
65 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
71 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
72 ORR r11, r11, r7, LSL r2 ; factor in the index number
74 SUBS r9, r9, #1 ; decrement the way number
80 ADD r10, r10, #2 ; increment the cache number
117 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
120 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
126 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
127 ORR r11, r11, r7, LSL r2 ; factor in the index number
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/
Dv7.s89 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
92 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
98 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
99 ORR r11, r11, r7, LSL r2 ; factor in the index number
101 SUBS r9, r9, #1 ; decrement the way number
107 ADD r10, r10, #2 ; increment the cache number
144 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
147 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
153 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
154 ORR r11, r11, r7, LSL r2 ; factor in the index number
[all …]
DMP_SCU.s20 ; Returns the number of CPUs in the Cluster
27 AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/
Dv7.s89 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
92 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
98 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
99 ORR r11, r11, r7, LSL r2 ; factor in the index number
101 SUBS r9, r9, #1 ; decrement the way number
107 ADD r10, r10, #2 ; increment the cache number
144 ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
147 ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
153 ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11
154 ORR r11, r11, r7, LSL r2 ; factor in the index number
[all …]
DMP_SCU.s20 ; Returns the number of CPUs in the Cluster
27 AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/example_build/
Dv7.S101 ANDS r4, r4, r1, LSR #3 @ R4 is the max number on the way size (right aligned)
104 ANDS r7, r7, r1, LSR #13 @ R7 is the max number of the index size (right aligned)
110 ORR r11, r10, r9, LSL r5 @ factor in the way number and cache number into R11
111 ORR r11, r11, r7, LSL r2 @ factor in the index number
113 SUBS r9, r9, #1 @ decrement the way number
119 ADD r10, r10, #2 @ increment the cache number
159 ANDS r4, r4, r1, LSR #3 @ R4 is the max number on the way size (right aligned)
162 ANDS r7, r7, r1, LSR #13 @ R7 is the max number of the index size (right aligned)
168 ORR r11, r10, r9, LSL r5 @ factor in the way number and cache number into R11
169 ORR r11, r11, r7, LSL r2 @ factor in the index number
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_boot.a64251 ubfx w4, w1, #3, #10 // w4 = max way number, right aligned
253 lsl w9, w4, w5 // w9 = max way number, aligned to position in DC operand
254 lsl w16, w8, w5 // w16 = amount to decrement way number per iteration
256 ubfx w7, w1, #13, #15 // w7 = max set number, right aligned
257 lsl w7, w7, w2 // w7 = max set number, aligned to position in DC operand
258 lsl w17, w8, w2 // w17 = amount to decrement set number per iteration
260 orr w11, w10, w9 // w11 = combine way number and cache number...
261 orr w11, w11, w7 // ... and set number for DC operand
263 subs w7, w7, w17 // Decrement set number
265 subs x9, x9, x16 // Decrement way number
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/
Dtx_thread_smp_core_get.mip39 /* This function gets the currently running core number and returns it.*/
68 and $2, $2, 0xFF # Isolate the VPE number
Dtx_thread_smp_current_state_get.mip72 sll $25, $25, 2 # Build index based on VPE number
Dtx_thread_smp_current_thread_get.mip71 sll $25, $25, 2 # Build index based on VPE number
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_smp_core_get.S68 and $2, $2, 0xFF # Isolate the VPE number
Dtx_thread_smp_current_state_get.S72 sll $25, $25, 2 # Build index based on VPE number
Dtx_thread_smp_current_thread_get.S71 sll $25, $25, 2 # Build index based on VPE number
Dtx_thread_smp_initialize_wait.S93 sll $8, $8, 2 # Build index based on VPE number
/ThreadX-v6.4.1/.github/
DPULL_REQUEST_TEMPLATE.md3 - [ ] Updated function header with a short description and version number
/ThreadX-v6.4.1/utility/rtos_compatibility_layers/OSEK/
Dthreadx_osek_readme.txt107 Since OSEK requires a static allocation methodology, the number of available OSEK object
110 Maximum number of tasks: 32
111 Maximum number of internal resources: 8
112 Maximum number of external resources: 16
113 Maximum number of alarms: 16
114 Maximum number of counters: 16
115 Maximum number of events: 32
116 Maximum number of category 2 ISRs: 8
/ThreadX-v6.4.1/utility/rtos_compatibility_layers/posix/
Dreadme_threadx_posix.txt49 that has at least the following number of bytes:
59 define the number of POSIX objects supported by the POSIX Wrapper (default
68 POSIX_MAX_QUEUES 32 /* maximum number of simultaneous POSIX
73 PTHREAD_THREADS_MAX 256 /* define the maximum number of simultaneous
76 POSIX_MAX_MUTEX 32 /* define the maximum number of simultaneous
228 Most functions can provide an error number. The means by which each function
230 provide the error number in a variable accessed through the symbol posix_errno.
231 While other functions return an error number directly as the function value. Functions
239 Each pthread has its own error number, which can be obtained through a
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_caches2.mip169 // Isolate L2 Associativity (number of ways)
172 add a1, 1 // Decode L2 number of ways
174 mul a3, a3, a1 // Get total number of sets (sets per way * number of ways)
208 // Isolate L3$ Associativity (number of ways)
211 add a1, 1 // Decode L3 associativity (number of sets)
212 mul a3, a3, a1 // Compute total number of sets
Dstart.mip344 /* For all VPEs, store the cpu number into the UserLocal field so it is easy to pickup. */
348 /* Save the stack pointer in the array indexed by cpu number. */
374 la $8, _tx_thread_smp_detected_cores # Build address of total number of cores detected
424 move a0, r23_cpu_num // main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
425 move a1, r8_core_num // main(arg1) is the core number.
426 move a2, r9_vpe_num // main(arg2) is the vpe number.
427 addiu a3, r20_more_vpes, 1 // main(arg3) is the number of vpe on this core.
430 move s0, r23_cpu_num // main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
440 // Main returns the "cpu" number
Dinit_gpr.mip68 // and loop back to next_shadow_set to start the next loop and the next lowest set number.
111 …, -1 // Since the code started with the highest set number this decrements to the next lower numb…
/ThreadX-v6.4.1/ports/arc_hs/metaware/example_build/sample_threadx/
Dsample_threadx.cmd7 //number of exceptions and interrupts
/ThreadX-v6.4.1/ports/arc_em/metaware/example_build/sample_threadx/
Dsample_threadx.cmd7 //number of exceptions and interrupts
/ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/
Dsample_threadx.cmd7 //number of exceptions and interrupts
/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/src/
Dtx_thread_smp_core_get.a6450 /* This function gets the currently running core number and returns it.*/

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