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/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/
Dtx_zynqmp_low_level.c141 static uint64_t mmu_tbl1[0x400]; variable
176 mmu_tbl0[0] = ((uint64_t) mmu_tbl1) + 0x3; in mmu_tbl_init()
178 mmu_tbl0[1] = ((uint64_t) mmu_tbl1) + 0x1000 + 0x3; in mmu_tbl_init()
185 mmu_tbl1[i] = sect + 0x3; in mmu_tbl_init()
191 mmu_tbl1[i] = sect + MMU_RESERVED; in mmu_tbl_init()
196 mmu_tbl1[i] = sect + MMU_DEVICE; in mmu_tbl_init()
203 mmu_tbl1[i] = sect + MMU_MEMORY; in mmu_tbl_init()
208 mmu_tbl1[i] = sect + MMU_RESERVED; in mmu_tbl_init()
214 mmu_tbl1[i] = sect + MMU_DEVICE; in mmu_tbl_init()
219 mmu_tbl1[i] = sect + MMU_DEVICE; in mmu_tbl_init()
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/ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/tgt/
Dstandalone_ram.ld46 .mmu_tbl1 ALIGN(4096) : > .