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/ThreadX-v6.4.1/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a35/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports/cortex_a75/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports/cortex_a76/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports/cortex_a76ae/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports/cortex_a65ae/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]
/ThreadX-v6.4.1/ports/cortex_a77/ac6/example_build/sample_threadx/
DGICv3_gicd.c104 void EnableSPI(uint32_t id) in EnableSPI() argument
111 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); in EnableSPI()
112 id &= 32 - 1; in EnableSPI()
114 gicd.GICD_ISENABLER[bank] = 1 << id; in EnableSPI()
119 void DisableSPI(uint32_t id) in DisableSPI() argument
126 bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); in DisableSPI()
127 id &= 32 - 1; in DisableSPI()
129 gicd.GICD_ICENABLER[bank] = 1 << id; in DisableSPI()
134 void SetSPIPriority(uint32_t id, uint32_t priority) in SetSPIPriority() argument
141 bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); in SetSPIPriority()
[all …]

12345678910>>...13