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/ThreadX-v6.4.1/ports/arm9/gnu/example_build/
Dreset.S52 LDR pc, UNDEFINED @ Undefined handler
53 LDR pc, SWI @ Software interrupt handler
54 LDR pc, PREFETCH @ Prefetch exception handler
55 LDR pc, ABORT @ Abort exception handler
56 LDR pc, RESERVED @ Reserved exception handler
57 LDR pc, IRQ @ IRQ interrupt handler
58 LDR pc, FIQ @ FIQ interrupt handler
63 .word __tx_undefined @ Undefined handler
65 .word __tx_swi_interrupt @ Software interrupt handler
67 .word __tx_prefetch_handler @ Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r4/gnu/example_build/
Dreset.S52 LDR pc, UNDEFINED @ Undefined handler
53 LDR pc, SWI @ Software interrupt handler
54 LDR pc, PREFETCH @ Prefetch exception handler
55 LDR pc, ABORT @ Abort exception handler
56 LDR pc, RESERVED @ Reserved exception handler
57 LDR pc, IRQ @ IRQ interrupt handler
58 LDR pc, FIQ @ FIQ interrupt handler
63 .word __tx_undefined @ Undefined handler
65 .word __tx_swi_interrupt @ Software interrupt handler
67 .word __tx_prefetch_handler @ Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r5/gnu/example_build/
Dreset.S52 LDR pc, UNDEFINED @ Undefined handler
53 LDR pc, SWI @ Software interrupt handler
54 LDR pc, PREFETCH @ Prefetch exception handler
55 LDR pc, ABORT @ Abort exception handler
56 LDR pc, RESERVED @ Reserved exception handler
57 LDR pc, IRQ @ IRQ interrupt handler
58 LDR pc, FIQ @ FIQ interrupt handler
63 .word __tx_undefined @ Undefined handler
65 .word __tx_swi_interrupt @ Software interrupt handler
67 .word __tx_prefetch_handler @ Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/arm11/gnu/example_build/
Dreset.S52 LDR pc, UNDEFINED @ Undefined handler
53 LDR pc, SWI @ Software interrupt handler
54 LDR pc, PREFETCH @ Prefetch exception handler
55 LDR pc, ABORT @ Abort exception handler
56 LDR pc, RESERVED @ Reserved exception handler
57 LDR pc, IRQ @ IRQ interrupt handler
58 LDR pc, FIQ @ FIQ interrupt handler
63 .word __tx_undefined @ Undefined handler
65 .word __tx_swi_interrupt @ Software interrupt handler
67 .word __tx_prefetch_handler @ Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r4/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r5/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_a8/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_a5/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_a9/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r7/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_a7/ghs/example_build/
Dreset.arm10 LDR pc,UNDEFINED # Undefined handler
11 LDR pc,SWI # Software interrupt handler
12 LDR pc,PREFETCH # Prefetch exception handler
13 LDR pc,ABORT # Abort exception handler
14 LDR pc,RESERVED # Reserved exception handler
15 LDR pc,IRQ # IRQ interrupt handler
16 LDR pc,FIQ # FIQ interrupt handler
29 .data.w __tx_undefined # Undefined handler
31 .data.w __tx_swi_interrupt # Software interrupt handler
33 .data.w __tx_prefetch_handler # Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/xtensa/xcc/src/
Dxtensa_intr_wrapper.c64 void * handler; member
84 xt_handler handler; in xt_interrupt_wrapper() local
99 handler = (xt_handler) entry->handler; in xt_interrupt_wrapper()
101 (*handler)(entry->arg); in xt_interrupt_wrapper()
Dxtensa_intr.c92 void * handler; member
139 old = entry->handler; in xt_set_interrupt_handler()
142 entry->handler = f; in xt_set_interrupt_handler()
146 entry->handler = &xt_unhandled_interrupt; in xt_set_interrupt_handler()
/ThreadX-v6.4.1/utility/rtos_compatibility_layers/posix/
Dpx_internal_signal_dispatch.c78 VOID (*handler)(int); in internal_signal_dispatch() local
106 handler = target_thread -> signals.signal_func[id]; in internal_signal_dispatch()
109 if (handler) in internal_signal_dispatch()
113 (handler)((int) id); in internal_signal_dispatch()
/ThreadX-v6.4.1/ports/cortex_r4/iar/example_build/
Dtx_initialize_low_level.s151 B __tx_undefined ; Undefined handler
156 B __tx_swi_interrupt ; Software interrupt handler
161 B __tx_prefetch_handler ; Prefetch exception handler
166 B __tx_abort_handler ; Abort exception handler
171 B __tx_reserved_handler ; Reserved exception handler
206 BL _tx_timer_interrupt ; Timer interrupt handler
268 B __tx_fiq_handler ; FIQ interrupt handler
/ThreadX-v6.4.1/ports/cortex_r5/iar/example_build/
Dtx_initialize_low_level.s151 B __tx_undefined ; Undefined handler
156 B __tx_swi_interrupt ; Software interrupt handler
161 B __tx_prefetch_handler ; Prefetch exception handler
166 B __tx_abort_handler ; Abort exception handler
171 B __tx_reserved_handler ; Reserved exception handler
206 BL _tx_timer_interrupt ; Timer interrupt handler
268 B __tx_fiq_handler ; FIQ interrupt handler
/ThreadX-v6.4.1/ports/cortex_a8/ac5/example_build/
Dtx_initialize_low_level.s83 LDR pc,=__tx_undefined ; Undefined handler
84 LDR pc,=__tx_swi_interrupt ; Software interrupt handler
85 LDR pc,=__tx_prefetch_handler ; Prefetch exception handler
86 LDR pc,=__tx_abort_handler ; Abort exception handler
87 LDR pc,=__tx_reserved_handler ; Reserved exception handler
88 LDR pc,=__tx_irq_handler ; IRQ interrupt handler
89 LDR pc,=__tx_fiq_handler ; FIQ interrupt handler
236 B __tx_undefined ; Undefined handler
240 B __tx_swi_interrupt ; Software interrupt handler
244 B __tx_prefetch_handler ; Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r4/ac5/example_build/
Dtx_initialize_low_level.s83 LDR pc,=__tx_undefined ; Undefined handler
84 LDR pc,=__tx_swi_interrupt ; Software interrupt handler
85 LDR pc,=__tx_prefetch_handler ; Prefetch exception handler
86 LDR pc,=__tx_abort_handler ; Abort exception handler
87 LDR pc,=__tx_reserved_handler ; Reserved exception handler
88 LDR pc,=__tx_irq_handler ; IRQ interrupt handler
89 LDR pc,=__tx_fiq_handler ; FIQ interrupt handler
236 B __tx_undefined ; Undefined handler
240 B __tx_swi_interrupt ; Software interrupt handler
244 B __tx_prefetch_handler ; Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_r5/ac5/example_build/
Dtx_initialize_low_level.s83 LDR pc,=__tx_undefined ; Undefined handler
84 LDR pc,=__tx_swi_interrupt ; Software interrupt handler
85 LDR pc,=__tx_prefetch_handler ; Prefetch exception handler
86 LDR pc,=__tx_abort_handler ; Abort exception handler
87 LDR pc,=__tx_reserved_handler ; Reserved exception handler
88 LDR pc,=__tx_irq_handler ; IRQ interrupt handler
89 LDR pc,=__tx_fiq_handler ; FIQ interrupt handler
236 B __tx_undefined ; Undefined handler
240 B __tx_swi_interrupt ; Software interrupt handler
244 B __tx_prefetch_handler ; Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_a5/ac5/example_build/
Dtx_initialize_low_level.s83 LDR pc,=__tx_undefined ; Undefined handler
84 LDR pc,=__tx_swi_interrupt ; Software interrupt handler
85 LDR pc,=__tx_prefetch_handler ; Prefetch exception handler
86 LDR pc,=__tx_abort_handler ; Abort exception handler
87 LDR pc,=__tx_reserved_handler ; Reserved exception handler
88 LDR pc,=__tx_irq_handler ; IRQ interrupt handler
89 LDR pc,=__tx_fiq_handler ; FIQ interrupt handler
236 B __tx_undefined ; Undefined handler
240 B __tx_swi_interrupt ; Software interrupt handler
244 B __tx_prefetch_handler ; Prefetch exception handler
[all …]
/ThreadX-v6.4.1/ports/cortex_a9/iar/example_build/
Dtx_initialize_low_level.s166 B __tx_undefined ; Undefined handler
171 B __tx_swi_interrupt ; Software interrupt handler
176 B __tx_prefetch_handler ; Prefetch exception handler
181 B __tx_abort_handler ; Abort exception handler
186 B __tx_reserved_handler ; Reserved exception handler
219 BL _tx_timer_interrupt ; Timer interrupt handler
317 B __tx_fiq_handler ; FIQ interrupt handler
/ThreadX-v6.4.1/ports/arm9/iar/example_build/
Dtx_initialize_low_level.s166 B __tx_undefined ; Undefined handler
171 B __tx_swi_interrupt ; Software interrupt handler
176 B __tx_prefetch_handler ; Prefetch exception handler
181 B __tx_abort_handler ; Abort exception handler
186 B __tx_reserved_handler ; Reserved exception handler
219 BL _tx_timer_interrupt ; Timer interrupt handler
317 B __tx_fiq_handler ; FIQ interrupt handler
/ThreadX-v6.4.1/ports/cortex_a8/iar/example_build/
Dtx_initialize_low_level.s166 B __tx_undefined ; Undefined handler
171 B __tx_swi_interrupt ; Software interrupt handler
176 B __tx_prefetch_handler ; Prefetch exception handler
181 B __tx_abort_handler ; Abort exception handler
186 B __tx_reserved_handler ; Reserved exception handler
219 BL _tx_timer_interrupt ; Timer interrupt handler
317 B __tx_fiq_handler ; FIQ interrupt handler
/ThreadX-v6.4.1/ports/arm11/iar/example_build/
Dtx_initialize_low_level.s166 B __tx_undefined ; Undefined handler
171 B __tx_swi_interrupt ; Software interrupt handler
176 B __tx_prefetch_handler ; Prefetch exception handler
181 B __tx_abort_handler ; Abort exception handler
186 B __tx_reserved_handler ; Reserved exception handler
219 BL _tx_timer_interrupt ; Timer interrupt handler
317 B __tx_fiq_handler ; FIQ interrupt handler
/ThreadX-v6.4.1/ports/cortex_a7/iar/example_build/
Dtx_initialize_low_level.s166 B __tx_undefined ; Undefined handler
171 B __tx_swi_interrupt ; Software interrupt handler
176 B __tx_prefetch_handler ; Prefetch exception handler
181 B __tx_abort_handler ; Abort exception handler
186 B __tx_reserved_handler ; Reserved exception handler
219 BL _tx_timer_interrupt ; Timer interrupt handler
317 B __tx_fiq_handler ; FIQ interrupt handler

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